OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.

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Presentation transcript:

OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function

Gate-level modeling(1) The following gates are built-in types in the simulator and, nand, nor, or, xor, xnor First terminal is output, followed by inputs and a1 (out1, in1, in2); nand a2 (out2, in21, in22, in23, in24); buf, not One or more outputs first, followed by one input not N1 (OUT1, OUT2, OUT3, OUT4, INA); buf B1 (BO1, BIN);

buf/not buf inOut xx zx not inOut xx zx

Gate-level modeling(2) bufif0, bufif1, notif0, notif1: three-state drivers Output terminal first, then input, then control bufif1 BF1 (OUTA,INA,CTRLA); pullup, pulldown Put 1 or 0 on all terminals pullup PUP (PWRA, PWRB, PWRC); Instance names are optional ex: not (QBAR, Q)

bufif1/notif1 bufif1 01xz 0 z0LL 1 z1HH x zxxx z zxxx ctrl in notif1 01xz 0 z1HH 1 z0LL x zxxx z zxxx ctrl in

Example module MUX4x1 (Z, D0, D1, D2, D3, S0, S1); output Z; input D0, D1, D2, D3, S0, S1; not (S0BAR, S0), (S1BAR, S1); and (T0, D0, S0BAR, S1BAR), (T1, D1, S0BAR, S1), (T2, D2, S0, S1BAR), (T3, D3, S0, S1); nor (Z, T0, T1, T2, T3); endmodule 4 X 1 multiplexer circuit

OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function

Data-flow modeling(1) Models behavior of combinational logic Assign a value to a net using continuous assignment Examples: wire [3:0] Z, PRESET, CLEAR; assign Z = PRESET & CLEAR; wire COUT, CIN; wire [3:0] SUM, A, B; assign {COUT, SUM} = A + B + CIN;

Data-flow modeling(2) Left-hand side (target) expression can be: Single net (ex: Z) Part-select (ex: SUM[2:0]) Bit-select (ex: Z[1]) Concatenation of both (ex: {COUT, SUM[3:0]}) Expression on right-hand side is evaluated whenever any operand value changes Note: Concatenation example {A,1’b0} -> x2 {A,2’b0} -> x4 wire [7:0]A,B; wire [16:0]C; assign C={A,B};

Delay Delay between assignment of right-hand side to left-hand side assign #6 ASK = QUIET || LATE; //Continuous delay Netdelay wire #5 ARB; // Any change to ARB is delayed 5 time units before it takes effect If value changes before it has a chance to propagate, latest value change will be applied – Inertial delay