Silicon Programming--Physical Testing 1 Testing--physical faults: yield; s-a-0 and s-a-1 faults; justify and propagate

Silicon Programming--Physical Testing 2 Yield: will always be a function of the chip area Good yield requires a “clean” fabrication facility (“cleanroom”) It will also be influenced by layout and technology formally, yield Y is defined by Y = [good chips on wafer)/(total # chips)]*100% many models for yield have been proposed

Silicon Programming--Physical Testing 3 A = area, D = number of "lethal" defects per cm 2 (typically 1 to 5) Seed's model (large chips, yield < 30%): Y = exp (-(AD) 1/2 ) Murphy's model (small chips,yield > 30%): = [ (1 - exp(-AD)) / AD] 2 A recent more general model: Y =  1<=i<=N (1+  j (AjDiPij/c(i)) -c(i) i = ith type of defect j = jth module P ij = probability defect i will cause error in area j c(i) = constant to compute the density of type i defect

Silicon Programming--Physical Testing 4 physical fault models (we consider only faults affecting logic, not timing): single faults--combinational logic simple but effective models have been developed based on the idea of: short:two points which should not be connected are open:a connection which should be present is broken

Silicon Programming--Physical Testing 5 Some commonly used fault models: “stuck at” faults: short to ground: may make a point on the circuit appear "stuck at 0” (s-a-0) broken connection: may make a point appear "stuck at 0" or "stuck at 1” (s-a-1) bridging faults: short between two lines may "create" a new logic function this is usually called a bridging fault

Silicon Programming--Physical Testing 6 many faults can be detected by examining the circuit for single "stuck at" faults--either s-a-0 or s-a-1 we often assume there is only one fault; we can justify this by choosing to test modular units of the system in which the fault density implies that there is likely to be only one fault

Silicon Programming--Physical Testing 7 example: if the point detected at f1 is s-a-0, the output o will always be 0 if f1 does not exist but f2 is s-a-0, the output o will also always be o the input x1 = 1 would detect f1 if z is measured the inputs x1 = x2 = 1 would detect f2 if f1 is not present but f2 is s-a-0 x1 = x2 = 0 would detect neither f1 nor f2 f2 f1 o x2 x1 z

Silicon Programming--Physical Testing 8 to detect a fault f we must input test vectors t at the “primary inputs” (PI) which activate f, i.e., which make output o| f (o given f) different from output o| ~f (o given not f) Let us denote these outputs by o f and o respectively we must also make sure the error caused by f is propagated to a primary output (PO) of the module, i.e., that there is a path sensitized to the fault point to some primary output in the circuit above, if o is anded with 0 (ground) before being output, then neither f1 nor f2 would be detected. If an input vector t and a sensitized path for a fault f exist, the fault is detectable. Otherwise it is said to be undetectable.

Silicon Programming--Physical Testing 9 Example: consider only combinational circuits, composed of AND, OR, NOT, NAND, NOR gates. We want to test for single s-a-0 or s- a-1 faults. Tasks: 1. activate ("excite") the fault 2. propagate fault to a primary output _ logic values:1 = 1/1; 0 = 0/0; D = 1/0; D’ = 0/1; X (D represents a signal that is 1 in a fault-free circuit and 0 in a faulty circuit, and D’ is defined similarly). truth tables:

Silicon Programming--Physical Testing 10 Composite logic values (examples): inputNOT inputsAND 0/010/0 any0/0 1/10 1/11/11/1 DD’1/1DD XX1/1D’D’ 1/1XX DDD DD’0 DXX D’D’D’ D’XX XXX (1 = 1/1; 0 = 0/0;D = 1/0; D’ = 0/1)

Silicon Programming--Physical Testing 11 Testing for a line L s-a-v in a fanout-free circuit: controlling value: the controlling value c of a gate is an input which determines its value regardless of the other inputs: ex: the controlling value for AND is c = 0. What about NAND? OR? NOR? inversion: the inversion or inversion parity i of a path is the number (modulo 2) of inverting gates (NAND,NOR,NOT) along the path the inversion of a gate is: 1 for NAND,NOR,NOT 0 for AND,OR note that if an input of a gate (AND,OR,NAND,NOR) is its controlling value c and i is its inversion then its output is c XOR i ex: if 0 is input to AND, output is 0 XOR 0 = 0 if 1 is input to OR, output is 1 XOR 0 = 1

Silicon Programming--Physical Testing 12 Basic algorithm to test L s-a-v: begin set all values to x Justify(L,v’) //set inputs so that line will be set to v’ if v = 0 then propagate (L,D) //propagate 1/0 (correct/faulty values) else propagate (L,D’) //propagate 0/1 (correct/faulty values) end

Silicon Programming--Physical Testing 13 "justify” algorithm--find PI values to set value of line L: Justify (L,val) begin set L to val if L is a PI then return else c = controlling value of L i = inversion of L inval = val xor i if (inval = c') then for every input j of L justify (j,inval) else begin select one input j of L justify (j,inval) end

Silicon Programming--Physical Testing 14 “propagate” algorithm: propagate the L value to a PO propagate (L, err) //err is D (1/0) or D’ (0/1) begin set L to err if L is PO then return else k = fanout of L c = controlling value of k i = inversion of k for every input j of k other than L justify (j, c') propagate (k, err xor i) end

Silicon Programming--Physical Testing 15 Example: a b c d g e f s-a-0 i h j Justify (f,L) and propagate (f,D): can input abcde =110x0 a=b=1 Justify(g,0) and propagate(h,D) c=0,e.g. Justify (i,1) e=0 L

Silicon Programming--Physical Testing 16 With fanout we may find conflicts: we can use backtracking to try to find a solution classical algorithm: “D algorithm”

Silicon Programming--Physical Testing 17 Other methods in use include: heuristic methods random test generation