ELEN468 Lecture 31 ELEN 468 Advanced Logic Design Lecture 3 Simulation and Testbench

ELEN468 Lecture 32 Overview Analog simulation Event-driven logic simulation Signal levels in logic simulation Propagation delay Inertial delay Testbench

ELEN468 Lecture 33 Analog Simulation Simulate waveforms Trace every signal at every time point at certain sampling rate Precise Long simulation time v t

ELEN468 Lecture 34 Logic Simulation At any moment, most signals are quiescent Very few signal levels At any simulation time, trace only signals with transitions (event) Propagate events from inputs toward outputs In a logic simulator An ordered list of “event-times” At each even time, an event queue is maintained

ELEN468 Lecture 35 Set of Logic Values Sometimes, {0, 1} is not enough a b 0 1 c If a = b = 0, c = ? If a = b = 1, c = ?

ELEN468 Lecture 36 Logic Values in Verilog 0: Logical 0 1: Logical 1 x: unknown z: high impedance and01ZX XX Z0XXX X0XXX

ELEN468 Lecture 37 X and Z a = b = 0: c = Z a = b = 1: c = X Initially, every line is X X is used in simulation. In real circuit, the value is determined by the circuit a b 0 1 c

ELEN468 Lecture 38 Simulation without Delay A = x B = x C = x D = x A = 1 B = 0 C = 0 D = 1 B = 1 C = 1 D = 0 A = 0 C = 0 D = 1 B = 0 t sim B A C D B A CD X X X XY

ELEN468 Lecture 39 Simulation with Delay A = x B = x C = x D = x A = 1 B = 0 C = 0 D = 1 B = 1 C = 1 D = 0 A = 0 C = 0 D = 1 B = 0 t sim B A C D B A C D X X X X

ELEN468 Lecture 310 Inertial Delay Delay is caused by charging and discharging node capacitors in circuit Gate delay and wire delay Pulse rejection If pulse with is less than delay, the pulse is ignored B A CD

ELEN468 Lecture 311 Example of De-scheduling A=x B=x C=x D=x A=1 B=0 C=1D=0 B=1 A=0 C=0 C=1 D=1 A B C D B A C D 32 T_sim

ELEN468 Lecture 312 Testbench Unit_Under_Test Stimulus generator Response monitor Design_Unit_Test_Bench

ELEN468 Lecture 313 Some New Keywords initial declares one-shot behaviors $monitor task is used to observe events $time returns simulation time $stop task stops execution and wait for interactive input $finish returns control to operating system

ELEN468 Lecture 314 Example of NAND Latch module Nand_Latch_1 (q, qbar, preset, clear); output q, qbar; input preset, clear; nand G1 (q, preset, qbar), G2 (qbar, clear, q); endmodule module Nand_Latch_1 (q, qbar, preset, clear); output q, qbar; input preset, clear; nand G1 (q, preset, qbar), G2 (qbar, clear, q); endmodule 1 1 G1 G2 q qbar preset clear PresetClearqqbar q_preqbar_pre

ELEN468 Lecture 315 Example of Testbench module test_Nand_Latch_1; reg preset, clear; wire q, qbar; Nand_Latch_1 M1 (q, qbar, preset, clear); // Instantiate UUT initial// Create response monitor $monitor ($time, "preset=%b clear=%b q=%b qbar=%b", preset, clear, q, qbar); initial begin// Create DUTB stimulus generator #10preset = 0; clear = 1; #10preset = 1; $stop;// Enter. to proceed #10clear = 0; #10clear = 1; #10preset = 0; end initial #60 $finish;// Finish simulation endmodule module test_Nand_Latch_1; reg preset, clear; wire q, qbar; Nand_Latch_1 M1 (q, qbar, preset, clear); // Instantiate UUT initial// Create response monitor $monitor ($time, "preset=%b clear=%b q=%b qbar=%b", preset, clear, q, qbar); initial begin// Create DUTB stimulus generator #10preset = 0; clear = 1; #10preset = 1; $stop;// Enter. to proceed #10clear = 0; #10clear = 1; #10preset = 0; end initial #60 $finish;// Finish simulation endmodule 1 1 G1 G2 q qbar preset clear

ELEN468 Lecture 316 Simulation Results t sim preset clear q qbar 0 preset = x clear = x q = x qbar = x 10 preset = 0 clear = 1 q = x qbar = x 11 preset = 0 clear = 1 q = 1 qbar = x 12 preset = 0 clear = 1 q = 1 qbar = 0 20 preset = 1 clear = 1 q = 1 qbar = 0 30 preset = 1 clear = 0 q = 1 qbar = 0 31 preset = 1 clear = 0 q = 1 qbar = 1 32 preset = 1 clear = 0 q = 0 qbar = 1 40 preset = 1 clear = 1 q = 0 qbar = G1 G2 q qbar preset clear