ITRS 2001 U.S. Design DTWG Meeting November 5, 2000 OUTCOMES (including extra slides from July 2000 International Design TWG meeting in SF)

Scenario: major increase in memory content

SOC Low Power Total Power Trend with No Low Power Solution Total Power Trend with Low Power Solution Scenario to keep 3W Low Power ITRS, meeting in Leuven 1st draft

Role of Design in ITRS Before 1999: –Addressed primarily hardware design and test tool issues and technologies –Largely ignored 1999 –Highlighted SoC trends and requirements –Received many requests from other TWGS

Role of Design in ITRS (cont’d) 2001 and Beyond –Needs to be involved in crosscut issues with other TWGs E.g., proposed crosscut panel on interconnect systems and optimization (including design, interconnect, packaging, PIDS, etc.) More bidirectional interactions with other TWGs –Needs to expand into new and important areas: Applications Architectures Optimized uses of process technology Analog/mixed signal and other technologies

Chapter Organization - Proposal “Context” Scope of Design Technology High-level summary of complexities (at level of “issues”) –Silicon trends/effects (include all of our ORTC lines !) –System complexity (drivers/architectures = what is being designed) –Methodology evolution Cost, productivity, quality, and other metrics of Design Technology Overview of Needs Driver classes and associated emphases (uP, ASIC, AMS/RF, SOC) MARK: –Analog/RF/MEMS –ASIC = compiled HDL  gates –High-volume custom = uP, DSP, embedded memories, reprogrammable… –SOC: high integration, low cost, low TTM Resulting needs (e.g., power, reprogrammability, cost-driven design) Summary of Difficult Challenges – by Driver Class Difficult Challenges Tables (visualize as many axes as possible) Detailed Statements of Needs and Potential Solutions System-Level Synthesis, Logic+Physical+Circuits, Functional Verification, Test, Design Process Metrics included; separate tables optional

Chapter Organization - Proposal Design Process: Don Cottrell ? infrastructure, design process metrics, … System-Level Design: Herman Designing the system Infrastructure for design IP reuse (precondition is CAD IP reuse?) Functional Verification: Carl System-level, RT-level, … Logical-Physical-Circuits: Andrew/Res/? Circuits includes “DSM effects”, hard-IP reuse/migration, Test: Mike/Tim Herman suggestion was: –{system, RTL, logic, xtor} X {spec, implement, verify} X {reuse}

Chapter Organization - Mapping “Context” Scope of Design Technology High-level summary of complexities (at level of “issues”) (Andrew, JohnD, Bill) Cost, productivity, quality, and other metrics of Design Technology (Ted, others TBD) Overview of Needs Driver classes and associated emphases (Don, Steve, Gary) Resulting needs (e.g., power, …, cost-driven design) (Jeff, Dennis, Res + AMS/RF (Al/John/Rick) + SOC (Res) + uP (Mark, Peter) + ASIC (JohnD/Andrew)) Summary of Difficult Challenges (All) Detailed Statements of Needs, Potential Solutions (All) Silicon (Physical, Synth/Logic, AMS/Circuits, Verif/Analysis groups) System (Test, Verification (digital, analog), System-Level groups) Design Process (Methodology/Metrics group)

Core Figures and Tables List: –Table – Issues taxonomy –Table – Metrics of Design Technology –Figure – Evolution of Design System Architecture –Figure – “Business Design Driver” Classes –Table(s) – Design Difficult Challenges (???) What does this look like ? –Additional Figures, Tables within the Detailed Statements of Needs and Potential Solutions sections Silicon System Design Process

Table X: Specific Design Challenges for Microprocessor Drivers near-term (>100nm) long-term (<100nm) criticality Design Process System-Level Design Functional Verification Logic/Phys/ Circuits Test *** have a graph like this for SOC, Analog/RF, and ASIC?? system only challenge #1 cross-cutting challenge between logic and system#1 cross-cutting challenge between systems, logic, circuit, PD, and system system only challenge #1 Logic only challenge #1 system only challenge #1 circuit only challenge #1 system only challenge #1

Action Items / Schedules Convergence on Core Figures, Needs Table(s) structure  5 column owners by November 20 th ; draft of 4 tables by November 30 th Report of ORTC line owners by November 30 th Teleconference December 13, 1pm (changed to 12:30pm) PST First drafts of new text: January 31 ? Meeting in February? (e.g., ISSCC Feb 5-7)