[M2] Traffic Control Group 2 Chun Han Chen Timothy Kwan Tom Bolds Shang Yi Lin Manager Randal Hong Wed. Nov. 11 Overall Project Objective : Dynamic Control The Traffic Lights

Status  Design Proposal  Chip Architecture  Behavioral Verilog Implementation  Size estimates  Floorplanning  Behavioral Verilog simulated  Gate Level Design  Component Layout/Simulation  Chip Layout  Complete Simulation

Data Input Initial Values Clock Operation T, Left-Turn Counter R, r, R_ L, r_ l Flow Control FSM Light Contro l FSM Selection

Old Version

Current Version

Arithmetic Unit Update  Status – 95%  Array Multiplier-100%  LVS + DRC clean  RCA Adder-100%  LVS + DRC clean  Simulations + finishing touches-0%  Analog Simulations with extractedRC fail  Last interconnects will be added when simulations are run and no buffers or changes need to be made

Arithmetic Unit Layout

Tom’s FSM  It’s messy, but it passes DRC and LVS  It could be smaller, so I will work to compress it more  No simulations yet

Tom’s FSM

Most Outputs Other Outputs Inputs

Light Control FSM Here is the log file shows where the error is.

Light Control FSM However, I found the transistor to check the parameter of it. It is different from what is presented in log file.

Light Control FSM  Found a fatal error when doing extracted RC simulations.  Still don’t know how to fix it.

Question ?