Intel IA-64 Architecture Chehun Kim Glenn Ramos

Contents *Pipelining - Stages of pipelining *Microprogramming *Interconnection Structures

Pipelining Pipelining - A means of introducing parallelism in to the essentially sequential nature of a machine-instruction program. IA 64 uses following methods for branches Prefetching with predication Prefetching with rotating registers Architectural support for software pipelining Modulo scheduling

IA-64 Instruction Pipeline -The Intel IA-64 Architecture’s pipeline is divided into 10 stages. -This design was developed for a single cycle ALU (4 ALU’s globally bypassed) and for low latency from data cache. IPGFETROTEXPRENWLDREGEXEDETWRB

IA-64 Pipeline IPGFETROTEXPRENWLDREGEXEDETWRB IPG – Instruction Pointer Generation FET – Fetch ROT - Rotate EXP – Expand REN – Rename WL.D – Word-Line Decode REG – Register Read EXE – Execute DET – Exception Detect WRB – Write-Back

IA-64 Pipeline The IA-64 instruction pipeline’s 10 stages are grouped into 4 phases. - Front End - Instruction Delivery - Operand Delivery - Execution

Front End -Front-end consists of stages IPG, FET and ROT. -This phase is responsible for fetching up to 32 bytes into a pre-fetch buffer. IPGFETROT EXPRENWLDREGEXEDETWRB

Instruction Delivery -This phase is composed of EXP and REN stages. -Dispersal of up to 6 instructions to 9 functional units occurs. -Implementation of registers for use in rotation and stacking occur. IPGFETROT EXPREN WLDREGEXEDETWRB

Operand Delivery - - This phase is composed of the WLD and REG stages. - - Register files are accessed and - - Accesses and updates a register scoreboard. This scoreboard is used to detect when individuals can proceed, so that a stall of 1 instruction in a bundle will not cause the entire bundle to stall. - - Check for dependencies. IPGFETROTEXPREN WLDREG EXEDETWRB

Execution -This phase consists of the EXE, DET and WRB stages. -In this phase, instructions are executed through the ALU and load/store units. -Exceptions are detected and NaTs are posted. -Instructions are retired and write-backs are performed. IPGFETROTEXPRENWLDREG EXEDETWRB

Microprogramming Intel IA-64 instruction set, EPIC, is a derived form of VLIW Intel IA-64 instruction set, EPIC, is a derived form of VLIW EPIC, standing for explicitly parallel instruction computing EPIC, standing for explicitly parallel instruction computing VLIW, standing for Very Long Instruction Word VLIW, standing for Very Long Instruction Word VLIW can perform multiple operations per cycle using horizontal microinstructions VLIW can perform multiple operations per cycle using horizontal microinstructions Remember that IA 64’s instruction word is 128 bits long and consists of 3 instructions Remember that IA 64’s instruction word is 128 bits long and consists of 3 instructions

Interconnection Structure

The processor uses a multidrop, shared system bus to provide four-way glueless multiprocessor system support. The processor uses a multidrop, shared system bus to provide four-way glueless multiprocessor system support. The 64-bit system bus uses a source-synchronous data transfer to achieve 266-Mtransfers/ s, which enables a bandwidth of 2.1 Gbytes/s. The 64-bit system bus uses a source-synchronous data transfer to achieve 266-Mtransfers/ s, which enables a bandwidth of 2.1 Gbytes/s. The combination of these features makes the Itanium processor system a scalable building block for large multiprocessor systems. The combination of these features makes the Itanium processor system a scalable building block for large multiprocessor systems.

Interconnection sturcture Source Synchronous Mode Source Synchronous Mode In source synchronous mode, the clock to data phase relationship at the input pins is maintained at the clock and data ports of the IOE input register. This mode is recommended for source synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as the same I/O standard is used. In source synchronous mode, the clock to data phase relationship at the input pins is maintained at the clock and data ports of the IOE input register. This mode is recommended for source synchronous data transfers. Data and clock signals at the IOE experience similar buffer delays as long as the same I/O standard is used. Multidrop Bus System Multidrop Bus System In multidrop bus systems when one device transmits, all others within range can receive In multidrop bus systems when one device transmits, all others within range can receive

Summary Pipeline Pipeline IA 64 has 10 stages IA 64 has 10 stages Microprogramming Microprogramming EPIC EPIC Interconnection Structure Interconnection Structure IA 64 uses source-synchronous data transfer IA 64 uses source-synchronous data transfer The processor uses a multidrop, shared system bus The processor uses a multidrop, shared system bus

Sources