Computer Architecture Lecture 10 EXCEPTIONS AND INTERRUPTS

Exceptions and Interrupts Exception handling is a programming language construct or computer hardware mechanism designed to handle the occurrence of some condition that changes the normal flow of execution. The condition is called an exception. Alternative concepts are interrupt, signal and event handling. In general, current state will be saved in a predefined location and execution will switch to a predefined handler (subroutine/procedure). Depending on the situation, the handler may later resume the execution at the original location, using the saved information to restore the original state. For example, an exception which will usually be resumed is a page fault, while a division by zero usually cannot be resolved transparently. (Wikipedia)

Common Exceptions I/O Device Request Integer Arithmetic Overflow FP Arithmetic Anomaly Page Faults Memory Protection Violation Undefined Instruction Power Failure etc

Characterizing Exceptions Synchronous vs. Asynchronous User Requested (system calls)/Coerced (mouse click) Maskable vs. Non-maskable Within / Between Instructions Resume-able/Terminate

Resumable Shut pipeline by converting all instruction after the instruction causing exception to NOP Save processor state Call Handler Resume State Precise Exception ???

MIPS Interrupts IF – Page Fault, MPV ID – Undefined or Illegal Op Code EX – Arithmetic MEM – Same as IF WB – None

MULTIPLE CYCLE PIPELINES

Single Cycle Computer Single Clock Cycle IF ID EXE WB (One Big Clock Cycle to Accommodate Longest Latency) IF ID EXE WB Single Clock Cycle

Multiple Cycle Computers IF ID EX WB All Instruction Go through the Processing One-by-One

Classic 5-Stage Integer Pipeline IF ID EX Mem WB Almost 1 CPI except for LUD and Branch Hazards

A Multiple Cycle Pipeline Register File (Integer/FP) EX FP ADD IF ID Mem WB FP Multiply Register File (Integer/FP) Divide Register File

Multiple Cycle Floating Point Pipeline EX Mem WB IF ID A 1 2 3 4 M .. 7 Divide Function Unit Latency Initiation /Re-Issue Interval Integer ALU 1 Load/Store FP Add 3 FP/Int Multiply 6 FP/Int Divide 24 25

Forwarding ALU/FP Instructions EX Mem WB IF ID A 1 2 3 4 M .. 7 Divide

Example 1 Without Forwarding With Forwarding L.D F10,0(R2) IF ID EXE MEM WB ADD.D F0,F1,F10 A1 A2 A3 A4 With Forwarding L.D F10,0(R2) IF ID EXE MEM WB ADD.D F0,F1,F10 A1 A2 A3 A4

EXAMPLE 2 ADD.D F0,F1,F2 ADD.D F5,F6,F7 ADD.D F0,F1,F2 ADD.D F5,F6,F0 IF ID A1 A2 A3 A4 ME WB ADD.D F5,F6,F7 ADD.D F0,F1,F2 IF ID A1 A2 A3 A4 ME WB ADD.D F5,F6,F0 I D

EXAMPLE 3 DIV.D F0,F1,F2 ADD.D F5,F6,F7 IF ID D I V 1 D I V 2 D I V 3 o D I V 24 ME WB ADD.D F5,F6,F7 DIV Unit is not Pipelined. So second instruction waits in ID stage although it is independent.

Example 4 - Out Of Order Execution Note All Instructions Independent L.D F10,0(R2) IF ID EXE MEM WB ADD.D F0,F1,F2 A1 A2 A3 A4 ADDI R5, R5, 10 Mul.D F9,F6,F7 M1 M2 M3 M4 M5 M6 M7 Add R3,R9,R10 Sub R7,R8,R10 Out Of Order Completion

Example 5 Clock Cycle Number Structural Hazard 1 2 3 4 5 6 7 8 9 10 11 Mul.D IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB o o o EX EXE Add.D A1 A2 A3 A4 L.D Structural Hazard

Example 6 - WAW MUL.D F3,F1,F2 IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB 8 9 10 11 12 13 MUL.D F3,F1,F2 IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB ADD.D F1,F5,F4 A1 A2 A3 A4 MUL.D F3,F9,F12 Reg Busy bit in Register File A particular processor – it waits in ID stage in case of WAW not in WB, Page A-54, Paragraph 2

Example 7 L.D F4, 0(R2) MUL.D F0,F4,F6 ADD.D F2,F0,F8 S.D F2,0(R2)

Example 8 - EXCEPTIONS DIV.D F0,F1,F2 ADD.D F10,F10,F8 SUB.D F12,F12,F14

Data Hazards RAW Hazard WAW Hazard WAR Hazard ADD.D F3, F1, F2 SUB.D F5, F6, F3 WAW Hazard DIV.D F3, F1, F2 SUB.D F3, F6, F5 WAR Hazard DIV.D F3, F1, F2 SUB.D F5, F6, F3 ADD.D F3, F6, F7

TOO MANY ID STAGE STALLS – SOLUTION?

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