Random Number Generator Dimtriy Solmonov W1-1 David Levitt W1-2 Jesse Guss W1-3 Sirisha Pillalamarri W1-4 Matt Russo W1-5 Design Manager – Thiago Hersan

A Quick Review Applications: encryption, gambling, personal computers, etc. Goal: faster random number generation than current software. Algorithm: –1028 bit seed fed into RAM –Feedback loop repeats 256 times to hash the seed and produce a pseudorandom number. –Two stage, five clocks per stage pipeline.

Status Last Time… C implementation Architecture Behavioral Verilog Datapath design This Week Finished Simulation Gate-Level Design Preliminary Floorplan In Process…  Schematic Unfinished Layout Extraction, LVS, post-layout simulation

Design Decisions Finalized interface between chip and outside world. Sense amps on SRAM

Chip Interface 64 IO pins for seed, random number. Other inputs: –Reset –Generate –Read –Clock Other outputs: –Ready –Done Design Decisions 2

Sense Amps Problem with bus charge time. Amplifiers that detect small changes in voltage and quickly ramp them up to high voltage. Design Decisions 3

32 Bit Adder Three adders execute 256 times each to generate one number. Hybrid carry skip, carry look ahead, carry select…… Fast and low power. Chirca, Schulte, Glossner, et al. “A Static Low-Power, High-Performance 32- bit Carry Skip Adder”

Block Diagram 32-Bit Adder 2 CS4CS18CS6CS4 A[3:0]B[3:0]A[9:4]B[9:4] A[27:10]B[27:10] A[31:28]B[31:28] S[31:28]S[27:10]S[9:4]S[3:0] C[0]C’[4]C[10]C’[28]C[32]

First CS4 Block 32-Bit Adder 3

CS6 Block 32-Bit Adder 4

CS18 Block 32-Bit Adder 5

Second CS4 Block 32-Bit Adder 6

Other Progress Synthesis of gate level Verilog from behavioral FSM and other control logic. Updated transistor count. Further developed floor plan and rough sizes.

Transistor Count Block Name Original Estimate Transistor Count (Alpha 6) Current Transistor Count (Alpha 8) SRAM6, Fast Hybrid Adder x3 4, FSM and Datapath4,000FSM: 230 Datapath: 9600 Total14,00027,030

Floor Plan 725 um ²