CS 140L Lecture 4 Professor CK Cheng 10/22/02. 1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

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CS 140L Lecture 4 Professor CK Cheng 10/22/02

1)F-F 2)Shift register 3)Counter (Asynchronous) 4)Counter (Synchronous)

Flip flop FDCE D CE C CLR Q CLR CE D C Q 1 X X X X X No change Asynchronous Clear Inputs Output Clock Enable CLK = 0 CLK = 1

D Q CLK t t t t setup t hold D Q tcqtcq

2) 3 bit shift register D Q CLK D Q D Q 0 0 X X X 11 0 X X X Time Steps A B C D A B C D

3 bit counter (asynchronous) T Q CLK T Q T Q t A C B t t B C t A Assume A(0) = B(0) = C(0) = Time C B A