Lucas-Lehmer Primality Tester Presentation 2: Architecture Proposal February 1, 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: The Testing of Prime numbers

Status Finished –Project Chosen –C simulations –Behavioral Verilog –Structural Verilog –Floor Plan In Progress –Optimization of Structural Code To Do –Schematic Design –Layout –Simulations

Design Decisions Current Implementation: –Ripple Carry Adder –Serial Mod Multiplier –Barrel Shifter Future: –Carry End Around Adder –Use Sequential Logic

Adder Options Parallel-prefix Adders –Serial-Prefix, which is the smallest but slowest –Sklansky parallel-prefix, which is the fastest but lager End-around Carry-Adders –Some take 2 propagations in series, which is slow –Faster ones require two adders and a multiplexer, which is big

Modulo Multiply (2 n -1) Has to do with partial products The algorithm calls for a Mod every time that there is a chance Example: Mod X Leave Mod

Structural Verilog Code module mod_mult(out, x, y, mod, p); input [15:0] x, y, mod, p; output [15:0] out; wire [15:0] pp00, pp01, pp02, pp03, pp04, pp05, pp06, pp07, pp08, pp09, pp10, pp11, pp12, pp13, pp14, pp15; wire [15:0] ma0, ma1, ma2, ma3, ma4, ma5, ma6, ma7, ma8, ma9, ma10, ma11, ma12, ma13, ma14, maX; partial_product ppg00(pp00, x, y, {4'b0000}, mod, p); partial_product ppg01(pp01, x, y, {4'b0001}, mod, p); partial_product ppg02(pp02, x, y, {4'b0010}, mod, p); partial_product ppg03(pp03, x, y, {4'b0011}, mod, p); partial_product ppg04(pp04, x, y, {4'b0100}, mod, p); partial_product ppg05(pp05, x, y, {4'b0101}, mod, p); partial_product ppg06(pp06, x, y, {4'b0110}, mod, p); partial_product ppg07(pp07, x, y, {4'b0111}, mod, p); partial_product ppg08(pp08, x, y, {4'b1000}, mod, p); partial_product ppg09(pp09, x, y, {4'b1001}, mod, p); partial_product ppg10(pp10, x, y, {4'b1010}, mod, p); partial_product ppg11(pp11, x, y, {4'b1011}, mod, p); partial_product ppg12(pp12, x, y, {4'b1100}, mod, p); partial_product ppg13(pp13, x, y, {4'b1101}, mod, p); partial_product ppg14(pp14, x, y, {4'b1110}, mod, p); partial_product ppg15(pp15, x, y, {4'b1111}, mod, p); mod_add CMA00(ma0, pp00, pp01, mod); mod_add CMA01(ma1, ma0, pp02, mod); mod_add CMA02(ma2, ma1, pp03, mod); mod_add CMA03(ma3, ma2, pp04, mod); //mod_add CMA04(maX, ma3, 16'b1111_1111_1111_1101, mod); mod_add CMA05(ma4, ma3, pp05, mod); mod_add CMA06(ma5, ma4, pp06, mod); mod_add CMA07(ma6, ma5, pp07, mod); mod_add CMA08(ma7, ma6, pp08, mod); mod_add CMA09(ma8, ma7, pp09, mod); mod_add CMA10(ma9, ma8, pp10, mod); mod_add CMA11(ma10, ma9, pp11, mod); mod_add CMA12(ma11, ma10, pp12, mod); mod_add CMA13(ma12, ma11, pp13, mod); mod_add CMA14(ma13, ma12, pp14, mod); mod_add CMA15(ma14, ma12, pp15, mod); sub_16 lastadd(.out(out),.cout(nowhere),.xin(ma14),.yin(16'b10)); //assign out = (pp00+pp01+pp02+pp03+pp04+pp05+pp06+pp07+ // pp08+pp09+pp10+pp11+pp12+pp13+pp14+pp15-2) % mod; endmodule

Simulation Results Fully simulates Mersenne Primes up to 30 Using the algorithm below Numbers above 2 30 make the code overflow because of the squaring in the algorithm 2 P -1 is prime if and only if S p-2 is zero in this sequence: S 0 = 4, S N = (S N ) mod (2 P -1) S 0 = 4 S 1 = (4 * 4 - 2) mod 127 = 14 S 2 = (14 * ) mod 127 = 67 S 3 = (67 * ) mod 127 = 42 S 4 = (42 * ) mod 127 = 111 S 5 = (111 * ) mod 127 = 0 So for : Result says it is prime

Behavioral Simulation S0 = 4 S1 = (4 * 4 - 2) mod 127 = 14 S2 = (14 * ) mod 127 = 67 S3 = (67 * ) mod 127 = 42 S4 = (42 * ) mod 127 = 111 S5 = (111 * ) mod 127 = 0

Structural Simulation

Reg:P Mod Calc (1<<p)-1 Reg:2 P -1 Mod Serial Multiplier Counter 0:P-2 Reg =-2 Comparator Counter = P-2 Check 0 Reg =4 Block Diagram for Prime Numbers P Out 16 1

Mod Serial Multiplier Block Diagram multiplicandmultiplier Zero? Mod mult Mod add Register p 2 p -1 16

Transistor Counts ModuleTransistor Count FSM300 Mod Calc2500 Counter1600 Mod Multiply15300 Registers3000 Compare for zero36 Total22736

Block Area Estimates ModuleArea (μm 2 ) FSM3000 Mod Calc3500 Counter6000 Mod Multiply75000 Registers4000 Compare for zero100 Total91600

Floorplan Prime Logic Mod Multiplier Mod Adder FSM Memory

Metal Layers Local connections, Vdd, Gnd –Metal 1: Horizontal –Metal 2: Vertical Global Connections, Clk –Metal 3: Horizontal –Metal 4: Vertical

What’s Next Possibly modify design so that prime logic can be turned off Continue optimizing –Current code creates a design that is way too big Analyze power/size tradeoffs between adders Do Schematic Design

Questions?