Feb 12, 2004Tiger SHARC Memory Operations REV B 1 of 17 ENEL DSP Architectures Tiger SHARC Memory Operations

Feb 12, 2004Tiger SHARC Memory Operations REV B 2 of 17 Overview Architecture Overview IALU Features Data addressing Normal, broadcast, merged distribution Circular buffers DAB Bit reversing Parallel instructions

Feb 12, 2004Tiger SHARC Memory Operations REV B 3 of 17 References ADSP-TS101 TigerSHARC Processor Programming Reference, Rev 1, January 2003, Analog Devices. – Sections 1 and 6 A number of the figures in this presentation are based on figures found in the ADSP- TS101 TigerSHARC Processor Programming Reference.

Feb 12, 2004Tiger SHARC Memory Operations REV B 4 of 17 Architecture Overview X Register File 32 x 32 bit Y Register File 32 x 32 bit Y Compute Block X Compute Block DMA and Link Controllers SDRAM Controller & External Port Interfaces Access to program and two data operands without memory or bus constraints.

Feb 12, 2004Tiger SHARC Memory Operations REV B 5 of 17 IALU Features bit general registers + 1 status register + 8 dedicated registers for circular buffers Performs integer ALU operations and data addressing ALU instructions: ADD, SUB, ARS, LRS (right shifts only), ROT (left and right), AND NOT, NOT, OR, XOR, ABS, MIN, MAX, CMP Status flags: zero (Z), negative (N), overflow (V), carry (C) Instruction conditions: EQ, LT, LE, NEQ, NLT, NLE Instruction options: unsigned (U), circular buffer (CB), bit reverse (BR), computed jump (CJMP) Address related operations: data address generation, circular buffers, bit reverse, UREG moves, DAB control.

Feb 12, 2004Tiger SHARC Memory Operations REV B 6 of 17 Indirect Loads and Stores Absolute: –Immediate:XR0 = [0x34FFFFFC];; –Register + optional immediate or register update: XR0 = [J0];; XR0 = [J0 += 0x4];; XR0 = [J0 += J1];; Relative offset: –Immediate offsetXR0 = [J0 + 0x34FFFFFC];; –Register offsetXR0 = [J0+J1];;

Feb 12, 2004Tiger SHARC Memory Operations REV B 7 of 17 Immediate Extension Operations Provides capability for 32 bit immediate operands. Assembler automatically uses 2 nd instruction slot (programmer must only use 3 of the 4 instruction slots) Requires the instruction with immediate extension to be in the 1 st slot Example: XR0 = [0x34FFFFFC]; K2=[K1+1]; YR0 = YR1 +YR2;; Only 1 immediate extension allowed per instruction line Don’t have to use 32 bit immediate. An 8 bit immediate will fit into the 32 bit instruction. (15 bit immediate for Ureg direct load instructions)

Feb 12, 2004Tiger SHARC Memory Operations REV B 8 of 17 Normal, Broadcast, Merged Distribution NORMALBROADCASTMERGED SINGLE XRs = [Jm]XYRs = [Jm]XYRs = L[Jm] DUAL XRsd = L[Jm]XYRsd = L[Jm]XYRsd = Q[Jm] QUAD XRsq = Q[Jm]XYRsq = Q[Jm]

Feb 12, 2004Tiger SHARC Memory Operations REV B 9 of 17 Word DAB First access loads in nearest quad boundary Second access loads in correct value J1 = 0x

Feb 12, 2004Tiger SHARC Memory Operations REV B 10 of 17 Short Word DAB Can realign on 16 bit boundaries J0 = ADDRESS(iaInput);; J0 = J0 +5; XR3:0 = SDAB Q[J0 += 8];;

Feb 12, 2004Tiger SHARC Memory Operations REV B 11 of 17 Circular Buffers Implemented with index, modify, length and base registers Index registers must be from J3~J0 or K3 ~ K0 Modify register can be any register in the same IALU Length and base registers are dedicated registers JL3 ~ JL0 and JB3 ~ JB0 respectively.

Feb 12, 2004Tiger SHARC Memory Operations REV B 12 of 17 Circular Buffer Code Example JL = 0;; JB = 0x34FFFFC0; // need 4 cycle latency J0 = 0x34FFFFC0; // before using JL or JB J1 = 1; NOP XR0 = CB [J0 += J1];; XR1 = CB [J0 += J1];; XR2 = CB [J0 += J1];; XR3 = CB [J0 += J1];;// J0 = JB after this instr.

Feb 12, 2004Tiger SHARC Memory Operations REV B 13 of 17 Bit Reverse.section data1.var intput[8] = {0, 1, 2, 3, 4, 5, 6, 7};.section program J0 = ADDRESS(input); XR0 = BR[J0 += 0x2121] /* If we assume that “input” is located at 0x0200A5A5 then Data is loaded from 0x Instead of 0x0200C6C6

Feb 12, 2004Tiger SHARC Memory Operations REV B 14 of 17 IALU Instructions ALU Instructions Ureg indirect register load Dreg indirect register load and DAB opsUreg register transfer Ureg indirect register stores Dreg indirect register stores

Feb 12, 2004Tiger SHARC Memory Operations REV B 15 of 17 Parallel Instructions A couple of examples of restrictions from the over 20 restrictions that apply to IALU instructions: –Loading from and storing to the same register in the same instruction line gives unpredictable results –A line of instructions can contain at most 1 load immediate data to register or 1 Ureg to Ureg transfer Details of restrictions can be found on pages 1-36 to 1-46 of the TigerSHARC Programming Reference Resource tables on 1–29 to 1–35 can help sort out resource restrictions for a single instruction line Consider the following instruction: [J0+J4] = XR1; [K8+=k9]=XR3;;

Feb 12, 2004Tiger SHARC Memory Operations REV B 16 of 17 [J0+J4] = XR1; [K8+=k9]=XR3;;

Feb 12, 2004Tiger SHARC Memory Operations REV B 17 of 17 [J0+J4] = XR1; [K8+=k9]=XR3;;