Xilinx CPLDs and FPGAs Lecture L1.1

CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA

XC9500 CPLDs 5 volt in-system programmable (ISP) CPLDs 5 ns pin-to-pin 36 to 288 macrocells (6400 gates) Industry’s best pin- locking architecture 10,000 program/erase cycles Complete IEEE JTAG capability Function Block 1 JTAG Controller Function Block 2 I/O Function Block 4 3 Global Tri-States 2 or 4 Function Block 3 I/O In-System Programming Controller FastCONNECT Switch Matrix JTAG Port 3 I/O Global Set/Reset Global Clocks I/O Blocks 1

XC9500 Function Block To FastCONNECT From FastCONNECT 2 or 4 3 Global Tri-State Global Clocks I/O 36 Product- Term Allocator Macrocell 1 AND Array Macrocell 18 Each function block is like a 36V18 !

XC9500 Product Family 9536 Macrocells Usable Gates t PD (ns) Registers Max I/O Packages VQ44 PC44 PC84 TQ100 PQ100 PC84 TQ100 PQ100 PQ160 PQ100 PQ HQ208 BG352 PQ160 HQ208 BG

Xilinx function blocks –Each contains 18 macro cells –Each macro cell behaves like a GAL32V18 AND-OR array for sum-of-products 32 inputs and 18 outputs

Architecture of the Xilinx XC95108 CPLD

Each Xilinx macrocell contains a D flip-flop Controlled inverter

Each Xilinx macrocell contains a D flip-flop Note asynchronous preset x Note asynchronous reset y z

CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA

Block diagram of Xilinx Spartan IIE FPGA

Each Spartan IIE CLB contains two of these CLB slices

Xilinx Spartan-II FPGAs

Block RAM

Delay-Locked Loop

Phase-Locked Loop

CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA

Virtex FPGAs For info on Virtex 1000 boards, see

Virtex-II FPGAs

Virtex-II Pro FPGAs