Conference on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, 2006 The Selective Read-out Processor for the CMS Electromagnetic Calorimeter Irakli Mandjavidze DAPNIA, CEA Saclay, Gif-sur-Yvette, France

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Overview Motivation and Goals The CMS ECAL read-out system and SRP SRP Challenges SRP Design → Platform FPGAs → Xilinx Virtex-II Pro devices → Firmware → Optical communication channels Current Status Conclusive remarks

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Motivation and goals CMS DAQ capabilities → Total event size: 1 Mbyte Allowed average ECAL event size: 100 Kbyte → Data throughput of 100 Gbyte/s ECAL raw data → Size: 1.5 Mbyte → Bandwidth: kHz L1 trigger rate Reduction factor of almost 20 is necessary → Crystal zero suppression: non-linearity and degraded energy resolution Selective Read-Out → Define zones of interest on event-by-event basis → Read full precision data from channels within these zones → Apply strong zero suppression on the rest of channels

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, The ECAL Read-out System Trigger Selective read-out processor: SRP Front-end electronics Read-out High level triggers and DAQ Raw data 1.5 Mbyte Selected data Selective read-out flags Trigger tower flags 5 µs timing budget L1 Accept100 kHz 40 MHz 100 Kbyte ECAL Asynchronous hard real-time system

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Type of Selective Read-out Algorithms Sliding windows algorithm → Trigger towers (TT) are classified as SuppressedSingleCenter NNNNN N N N NNNNN N N N N NNN NNN NC Neighbors ETET Low High → Singles, centers, neighbors: full precision read-out → Suppressed: zero suppression read-out → Complemented by coarse grain data i.e. energy deposited in all TTs Reduction factor of 20 → detector performance: no noticeable degradation Low threshold (GeV) Event size (KB) High threshold 2 GeV ZS (0σ) ZS (1σ) ZS (2σ)

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, SRP Challenges Asynchronous operation at 100 kHz L1 trigger rate 5 µs timing budget High number of input / output channels → ~200 optical communication links 1.6 Gbit/s throughput per link Certain flexibility to allow changes and evolution of selective read-out algorithms Combine advances in technologies of → the programmable logic (FPGA) → the optical communication

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, SRP Architecture Compact system: single VME 6U crate → 12 identical VME64x compliant boards 3 boards covering each of 4 ECAL partitions Note: the SRP board is used also as SRP tester → VME-PCI interface board with a contol PC → Boindary Scan controller for remote firmware management Just one custom board to develop and maintain Half barrels - + End- cap + End- cap - VME-PCI interface Boundary Scan Controller

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, SRP Boards VME64x compliant board with PnP capability → 3 firmware : « barrel », « end-cap », « tester » sharing a bulk of VHDL code P1P2 VME buffers VME Serial links Algorithms Trigger IF FPGA Xilinx Virtex-II Pro xc2vp70-6-ff1704 Power supply Clock synthesizer Contrôleur JTAG FPROMs T T F Rx S R F Tx S R P Rx S R P Tx Parallel optics Throttling TTS Out O/E Trigger, timing, and control Cons., JTAG Aux. connector Trigger Interface

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, SRP Boards → 12 layers, 1.6mm thick → Up to 20 bidirectional optical communication links at 1.6 Gbit/s each → 40 differential pairs with 100Ω controlled impedance → Synthesizable clock → Monster FPGA with 1704-pin ball grid array package Reset Reload Stratus LEDs RS232 Trigger TTF SRF SRP Trigger throttle JTAG

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Platform FPGAs Xilinx 2vp70 Virtex-II Pro 2 PowerPC MHz 20 RocketIO transceivers up to 3 Gbit/s 18 kbit dual-port memories Flexible reconfigurable System-On-Chip Devices Programmable logic cells → combinatorial and synchronous Versatile IOs → Single ended and differential Hard IP cores → Clock management → Memory blocks → Serial transceivers → Embedded processor(s) Plus various soft IP cores → Microcontrollers, network IF... CPU DCM MGT MEMORYMEMORY

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Firmware System-on-Chip design: handy for debugging and monitoring → embedded 80 MHz PowerPC with 128 Kbyte memory stand-alone “C” applications for testing, debugging and monitoring → 32-bit slave interface on a 40 MHz peripheral bus SRP Barrel and Endcap: equivalent logic cells: 40% → 3.5 µs latency from L1 accept till SR flags delivered to the read-out SRP Tester: equivalent logic cells: 60% Plenty of resources for future enhancements Memory 128 KB Processor bus PowerPC 80 MHz Bridge RS232 console Slave interface SRP board 80 MHz pipeline logic 40 MHz 32-bit R/W Peripheral bus VME Optical IO Firmware organization

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Trigger-SRP and SRP-Read-out links Optical communication channels Fan-in/Fan-out modules Individual LC fibers 12-fiber MTP cables SerializerTx Trigger DeserializerRx Readout Rx Up to 12 deserializers in FPGA Tx Up to 12 serializers in FPGA SRP Small form factor pluggable transceivers Pluggable parallel optic modules

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, SRP-SRP links → are needed to exchange information on frontiers → passive optical cross-connect: all-to-all connectivity Optical communication channels

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Optical communication channels Measurements done with the LeCroy Serial Data Analyzer MPO/MPO cable 2m LC/LC cable 30 m Tx Serial Data Analyzer Parallel transmitter FDM BER ~0.8 UI eye opening → 0.65 is required for BER by specifications

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Some Photos Test system with prototypes → one card tests another LeCroy Serial Data Analyzer Control PC & Console for the embedded SoC Processor VME crate with the two prototypes

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Some Photos Test system with all 12 SRP boards → organized as 6 barrel and 6 tester boards Passive optical cross-connect VME crate with 12 boards

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Some Photos Barrel SRP boards installed in the CMS service cavern 6 barrel SRP boards Cross-connect & 12-fiber MPO cables Patch-panel & 12-fiber MPO cables Fan-in/Fan-out modules and individual LC fibers

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Summary All SRP boards produced and verified → spares + 2 completely operational prototypes → up to 100 kHz trigger rate → weeks of operation without communication link errors 6 barrel boards installed at CERN → commissioning underway 6 end-cap boards to be commissioned early in 2008 → together with trigger and read-out electronics 6 spare boards as development systems → 4 at CERN and 2 at Saclay Impatient to meet the very first collisions

on ''Physics at the Future Colliders'', Tbilisse, Georgia, October 22-28, Les mots de la fin... Just a little drop in the Sea(MS)... → Only one crate → 12 electronic boards but extremely attractive → Modern Platform FPGAs → Multi gigabit per second links → Parallel optics → System-on-chip design An insight of electronics to be used in HEP experiments at future colliders