CS 7810 Lecture 6 The Impact of Delay on the Design of Branch Predictors D.A. Jimenez, S.W. Keckler, C. Lin Proceedings of MICRO

Bimodal Predictor Branch PC 14 bits Table of 16K entries of 2-bit saturating counters

Global Predictor A single register that keeps track of recent history for all branches Branch PC 8 bits 6 bits Table of 16K entries of 2-bit saturating counters Also referred to as a two-level predictor

Local Predictor Branch PC Table of 16K entries of 2-bit saturating counters Table of 64 entries of 14-bit histories for a single branch Use 6 bits of branch PC to index into local history table 14-bit history indexes into next level A two-level predictor that only uses local histories at the first level

Tournament Predictors A local predictor might work well for some branches or programs, while a global predictor might work well for others Provide one of each and maintain another predictor to identify which predictor is best for each branch Tournament Predictor Branch PC Table of 2-bit saturating counters Local Predictor Global Predictor MUXMUX

Terminology GAG: Global history indexes into global array of saturating counters PAG: Per-address history indexes into global array of saturating counters GAP: Global history indexes into each PC’s private array of counters (gselect) PAP: Per-address history indexes into each PC’s private array of counters

Prediction Accuracy Vs. IPC

Fig.1 – IPC saturates at around 1.28, assuming single-cycle predictions A 2KB predictor takes two cycles to access – multi-cycle predictors can’t yield IPC > 1.0 (reduced fetch bandwidth) However, note that a single cycle predictor is within 10% of optimal IPC (might not be true for more aggressive o-o-o processors)

Long Latency Predictions Total branch latency C = d + (r x p) d = delay = 1 r = mpred rate = 0.04 p = penalty = 20 Always better to reduce d than r Note that correctly predicted branches are often not on the program critical path

Branch Frequency Branches are not as common as we think – on average, they occur every 6 instructions, but 61% of the time, there is at least 1 cycle of separation Branches can be treated differently, based on whether they can tolerate latency or not

Branch Predictor Cache The cache is a subset of the 3-cycle predictor and requires tags ABP provides a prediction if there is a cache miss 3-cycle PHT 1-cycle PHTTagsABP Xor of address and history Hit/Miss Prediction

Cascading Lookahead Prediction Use the current PC to predict where the next branch will go – initiate the look-up before you see that branch Use predictors with different latencies – when you do see the branch, use the prediction available to you You can use a good prediction 60% of the time and a poor prediction 40% of the time

Overriding Branch Predictor Use a quick-and-dirty prediction When you get the slow-and-clean prediction and it disagrees, initiate recovery action If prediction rates are 92% and 97%, 5% of all branches see a 2-cycle mispredict penalty and 3% see a 20-cycle penalty

Combining the Predictors? Lookahead into a number of predictors When you see a branch (after 3 cycles), use the prediction from your cache (in case of a hit) or the prediction from the regular 3-cycle predictor (in case of a miss) When you see the super-duper 5-cycle prediction, let it override any previous incorrect prediction

Latencies TechnologyABP Delay ABP Entries PHTC Entries PHT Delay PHT Entries 100nm11K K 35nm K

Results (Fig.8)

The cache doesn’t seem to help at all (IPC of 1.1!) (it is very surprising that the ABP and PHT have matching predictions most of the time) For the cascading predictor, the slow predictor is used 45% of the time and it gives a better prediction than the 1-cycle predictor 5.5% of the time The overriding predictor disagrees 16.5% of the time and yields an IPC of 1.2 – hmmm…

Alpha Predictor chooser PHT global predictor PHT local history PHT global history global history PC 512 entries 128 entries 3200 bits 128 entries

Alpha (EV8) 352Kb! 2-cycle access time – 4 predictor arrays accessed in parallel – overrides line prediction cycle mispredict penalty – 8-wide processor in-flight instructions

Predictor Sizes All tables are indexed using combinations of history and PC BIMG0G1Meta Prediction table16K64K Hysteresis table16K32K64K32K History length

2Bc-gskew Address Address+History BIM Meta G1 G0 Pred Vote

Rules On a correct prediction  if all agree, no update  if they disagree, strengthen correct preds and chooser On a misprediction  update chooser and recompute the prediction  on a correct prediction, strengthen correct preds  on a misprediction, update all preds

Design Choices Local predictor was avoided because you need up to 16 predictions in a cycle and it is hard maintaining speculative local histories  You have no control over local histories – will need 16-ported PHT  Since global history is common for all 16 predictions, you can control indexing into PHT They advocate the use of larger overriding predictors for future technologies

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