Placement-Centered Research Directions and New Problems Xiaojian Yang Amir Farrahi Synplicity Inc.

Topics u Basic Requirements u Mixed Block Standard-Cell Placement u Incremental Placement u Placement-In-Flow u Congestion/Routability u Timing Driven Placement u Other objectives

Basic Requirements u Large scale problem u Fixed-die with 50-80% density u Wirelength u Basic algorithms and methodologies ä Min-cut, Analytical, Annealing ä Clustering ä Multi-level ä Hierarchical

Placement with white space MCNC benchmarks Industrial designs

Mixed Mode Placement u Fixed Macros ä Non-rectangle placeable area ä Min-cut and annealing can be adjusted. What about quadratic approach? u Movable Macros ä Floorplanning macros then place standard-cells ä Clustering and floorplanning hard/soft macros ä Splitting hard macros to form standard-cell placement ä Modified partitioning --- cut hard macros ä Low utilization --- not packing-type floorplanning

Incremental Placement u Caused by various reasons ä Placement based logic optimization ä Clock tree construction ä Power rail / special nets construction ä ECO u Incremental Detailed Placement ä Highly constrained ä Minimum disturbance if the change is small ä Appropriate replacement based on the amount of change ä Measurement of the disturbance

Placement-In-Flow u Floor-Placer (Steve Teig, ISPD2002) ä Mixed macro standard-cell placement ä Floorplan with unfixed soft macros ä Placement with unfixed hard macros u Placement with Global Routing ä Change placement based on global routing results u Placement in Physical Synthesis ä Choose the “right” optimization in placement ä Priorities of placement objectives ä Positions of Global/Detailed placement ä Interleaving logic synthesis optimizations

Congestion/Routability u Transparent congestion management ä Caldwell/Kahng/Markov DAC2000 ä Congestion improvement if and only if required ä Tradeoff between congestion and wirelength/delay u Use of White space / Free space ä Uniform distribution ä routability-driven distribution (not too aggressive) u Routing resource aware placement ä Horizontal/vertical wires ä Blockages in routing layers

Timing u Avoid pure timing-driven placement ä May hurt other objectives ä Could focus on critical paths that can be easily fixed by logic changes u Focus: timing-driven placement with minor changes on the netlist ä Buffer insertion, Gate sizing, Gate replication u Transparent timing optimization ä Again, tradeoff between delay and routability ä Constraint-driven rather than minimization u Understanding the relationship between routability and timing ä Negative: reducing congestion increases critical path ä Netural: reducing congestion does not affect critical path ä Positive: reducing congestion brings better post-routing delay

Other Objectives u Power Driven Placement u Multi-voltage designs u Signal Integrity: Cross talk driven placement u IR-Drop Issue and Placement u Thermal Issue and Placement u Placement Constraints u High Density Design Placement u Multiple objectives in placement

Summary u Placement remains a challenging problem, and becomes more difficult with more constraints u There are always tradeoffs between placement objectives u Placement combined with other optimizations could gain more u Benchmarks are indispensable for academic research