RF Triangulator: Indoor/Outdoor Location Finding Architecture Proposal Giovanni Fonseca David Fu Amir Ghiti Stephen Roos Design Manager: Myron Kwai Overall Project Objective: Design a Radio-Frequency indoor/outdoor navigation system, utilizing the existing wireless infrastructure. Design Stage Objective: Implement structural Verilog description And Floorplanning

Status Behavioral complete and tested. Behavioral complete and tested. Structural complete except for floating point unit testing. Structural complete except for floating point unit testing. Began work on schematics. Began work on schematics.

Assumptions ► Assume that 12 bit Floating point would be precise for our computations. ► Assume that maps will be provided. ► Local subsections of the map will be loaded into the chip. ► Map data is limited by the capacity of the display device (PDA or cellphone etc).

Structural Verilog Results: t = 240 INPUTS: [ ID = 0000aaaabbbb SNRr = 80 clk|rst = (1|1) ] LOOKUP: [ ID = 0000aaaabbbb (X,Y) = ( 20, 30) (SNRt,SNRr) = ( 200, 80) ] NEWROW: [ ID = 0000aaaabbbb (X,Y) = ( 20, 30) (SNRt,SNRr) = ( 200, 300) ] ROW A : [ ID = (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 0) R(1) ] ROW B : [ ID = (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 0) R(0) ] ROW C : [ ID = (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 0) R(1) ] SAMPLA: [ Sample 1 = 0 Sample 2 = 0 Sample 3 = 0 Sample 4 = 0 Average = 0 ] SAMPLB: [ Sample 1 = 0 Sample 2 = 0 Sample 3 = 0 Sample 4 = 0 Average = 0 ] SAMPLC: [ Sample 1 = 0 Sample 2 = 0 Sample 3 = 0 Sample 4 = 0 Average = 0 ] QUEUE1: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE2: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE3: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE4: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] FLAGS : [ Update (A,B,C) = (0|0|0) Replace (A, B, C) = (0|1|0) DoLookup = 0 ] LKREG : [ LookupRow = 80 ] *OP: t = 260 INPUTS: [ ID = 0000aaaabbbb SNRr = 80 clk|rst = (1|1) ] LOOKUP: [ ID = 0000aaaabbbb (X,Y) = ( 20, 30) (SNRt,SNRr) = ( 200, 80) ] NEWROW: [ ID = 0000aaaabbbb (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 80) ] ROW A : [ ID = (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 0) R(1) ] ROW B : [ ID = 0000aaaabbbb (X,Y) = ( 20, 30) (SNRt,SNRr) = ( 200, 300) R(1) ] ROW C : [ ID = (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 0) R(0) ] SAMPLA: [ Sample 1 = 0 Sample 2 = 0 Sample 3 = 0 Sample 4 = 0 Average = 300 ] SAMPLB: [ Sample 1 = 300 Sample 2 = 300 Sample 3 = 300 Sample 4 = 300 Average = 300 ] SAMPLC: [ Sample 1 = 0 Sample 2 = 0 Sample 3 = 0 Sample 4 = 0 Average = 300 ] QUEUE1: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE2: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE3: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE4: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] FLAGS : [ Update (A,B,C) = (0|1|0) Replace (A, B, C) = (0|0|0) DoLookup = 0 ] LKREG : [ LookupRow = 80 ] *OP: t = 280 INPUTS: [ ID = 0000aaaabbbb SNRr = 80 clk|rst = (1|1) ] LOOKUP: [ ID = 0000aaaabbbb (X,Y) = ( 20, 30) (SNRt,SNRr) = ( 200, 80) ] NEWROW: [ ID = 0000aaaabbbb (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 80) ] ROW A : [ ID = (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 0) R(1) ] ROW B : [ ID = 0000aaaabbbb (X,Y) = ( 20, 30) (SNRt,SNRr) = ( 200, 300) R(1) ] ROW C : [ ID = (X,Y) = ( 0, 0) (SNRt,SNRr) = ( 0, 0) R(0) ] SAMPLA: [ Sample 1 = 0 Sample 2 = 0 Sample 3 = 0 Sample 4 = 0 Average = 245 ] SAMPLB: [ Sample 1 = 80 Sample 2 = 300 Sample 3 = 300 Sample 4 = 300 Average = 245 ] SAMPLC: [ Sample 1 = 0 Sample 2 = 0 Sample 3 = 0 Sample 4 = 0 Average = 245 ] QUEUE1: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE2: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE3: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] QUEUE4: [ ID = (X,Y) = ( 0, 0) SNRt = 0 ] FLAGS : [ Update (A,B,C) = (0|1|0) Replace (A, B, C) = (0|0|0) DoLookup = 0 ] LKREG : [ LookupRow = 80 ]

Transistor counts ModuleTransistors Lookup*2k Calc7k FPU12k Top 3 5k Total26k *14k with SRAM

Floorplan

FPU Block Diagram Figure 1*

Realistic Area Estimates FPU : micron^2 FPU : micron^2 Calc: micron^2 Calc: micron^2 Lookup : micron^2 Lookup : micron^2 Top 3: micron^2 Top 3: micron^2 Overall : micron^2 Overall : micron^2

Local versus global interconnect layers Use metal 1 and 2 for basic gates Use metal 1 and 2 for basic gates Use metal 3 and 4 for upper level and global routing Use metal 3 and 4 for upper level and global routing Metal Directionality and Porosity Have metal 1 and 3 go horizontally.Have metal 1 and 3 go horizontally. Metal 2 and 4 go vertically.Metal 2 and 4 go vertically.

Questions/Concerns We need more details on SRAM schematic. We need more details on SRAM schematic. We need to find ways to minimize transistor count. We need to find ways to minimize transistor count.

Acknowledgments Diagram 1 :