Mapping Petri Nets into Event Graphs. Alternative Implementations Activity World View Petri Net Formalism: Simple fundamental elements and behavior Concurrent.

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Presentation transcript:

Mapping Petri Nets into Event Graphs

Alternative Implementations Activity World View Petri Net Formalism: Simple fundamental elements and behavior Concurrent resource usage and contention Event Scheduling View Event Graph Formalism: Simple fundamental element and behavior Concurrency and contention - large model representations

Transitions become timed edges Places become conditional edges PN->EG MAPPING

PN->EG Mapping: eg. G/G/s queue PN: Q s T a T S A

PN->EG Mapping: eg. G/G/s queue PN: EG: Q s T a T S A {A--} {A++, Q++} {Q--, S--} {S++} T s a T

PN->EG Mapping: eg. G/G/s queue PN: EG: Q s T a T S A (S&Q) (A) (S&Q) {A--} {A++, Q++} {Q--, S--} {S++} T s a T

PN->EG Mapping: eg. G/G/s queue (S&Q) (A) (S&Q) {A--} {A++, Q++} {Q--, S--} {S++} T s a T Variable A is unnecessary!

PN->EG Mapping: eg. G/G/s queue (S&Q) { Q++} {Q--, S--} {S++} T s a T Empty Vertex is unnecessary!

PN->EG Mapping: eg. G/G/s queue (S&Q) { Q++} {Q--, S--} {S++} T s a T S&Q conditions redundant too...

PN->EG Mapping: eg. G/G/s queue (Q) (S) { Q++} {Q--, S--} {S++} T s a T Result: a conventional G/G/s queue EG model

P = set of Places, T = set of transitions in PN d(t) = delay time (RV) for transition t  T {Ip(t),Op(t)}= Set of Input and Output Places for t  T {It(p),Ot(p)}= Set of Input and Output Transitions for p  P Step 0.  p  P: define an integer state variable, X(p). Step 1.  t  T: create an edge (O(t), D(t)) with delay d(t). Step 2.  p  P with unique (It(p),Ot(p)) pair: create the edge (D(It(p)),O(Ot(p))) with the condition that all p  Ip(Ot(p)) are marked. (For inhibitor arcs these places must not be marked.) Step 3. Add State changes: for O(t), decrement X(p)  p  Ip(t); for D(t), increment X(p)  p  Op(t). PN  EG MAPPING Advanced homework: Confirm this or find a counter example.

Analytical Methods and Conditions PNs Reachabilty, decidability, liveness, and deadlock EGs State definition, event reduction, priorities, equivalence, boundary conditions, resource deadlock, MIP representations

COMMUNICATIONS BLOCKING (R1 needs empty buffer to Start) R1,R2 = Number of idle resources Q1,Q2 = Number of waiting jobs B = Number of empty buffer spaces... t a,t s1,t s2 = Arrival and processing times...

COMMUNICATIONS BLOCKING: Petri Net AQ1 R1 tata t s1 Q2 R2 B t s2 0 W Q1 = number of jobs waiting in queue 1 Q2 = number waiting in queue 2 R1 = idle resources for step 1 R2 = idle resources for step 2 B = available buffer slots

Each transition becomes a timed edge... tata AQ1 R1 tata t s1 Q2 R2 B t s2 0 W t s1 0t s2

Next, each place becomes a conditional edge... (ALL input places marked is condition) AQ1 R1 tata t s1 Q2 R2 B t s2 0 W (A) (Q1&R1&B) tata t s1 0t s2 ~ ~ ~ ~ ~ ~ ~ (Q1&R1&B) (Q2&R2) (W)

tata Mapping Petri Net to Event Graph Finally, increment and decrement tokens as state changes {A++, Q1++} {Q1--, R1--. B--} {A--}{R1++, Q2++} {R2-- Q2--} {R2++} AQ1 tata t s1 Q2 B t s2 0 W tata t s1 0t s2 ~ ~ ~ ~ ~ ~ ~ (Q1&R1&B) (Q2&R2) (W) R1R2 {W++ B++} {W--} (Q1&R1&B) (A)

{A++, Q1++} {Q1--, R1--. B--} {A--}{R1++, Q2++} {R2-- Q2--} {R2++} tata t s1 0t s2 ~ ~ ~ ~ ~ ~ ~ (Q1&R1&B) (Q2&R2) (W) {W++ B++} {W--} (Q1&R1&B) (A) Final Event Graph: How can this be simplified? (ref: Seila, et. al. Text)

{Q1++} {Q1--, R1--. B--} {R1 ++, Q2++} {R2-- Q2-- B++} {R2++} tata t s1 t s2 ~ ~ ~ ~ ~ (R1&B) (Q1&B) (R2) (Q2) (Q1&R1) A Simplified Event Relationship Graph

Implications PN analysis of Event Graphs State reachability Liveness Deadlock EG analysis of Petri Nets State space Model reduction Equivalence Boundary Conditions Resource Deadlock

Petri Net Simulator

t f t r t f t r Fail-Repair PN: EG: 0 0 a A B C D (A&!B) (D&B) (C) (D&B)

PN->EG Mapping Transformed EG Failure-Repair Model A++ B++ A-- B-- D-- C++ C-- D++ (A&&!B) (B&&D) (C) (A&&!B) (B&&D) D=3 // // // // // 0

PN->EG Mapping Reduced EG Failure-Repair Model {N- -} {N++} t f t r FailFix

EG -> PN Mapping Conditions: Need to have non-negative, integral state changes Test only for non-negativity of integers Needs to “edge bi-partite” pure-timed and pure- conditional edges alternate Single state change at each vertex - upstream of timed decrement, downstream of timed increment Expansion Algorithm of Yucesan and Schruben Add conditions upstream when breaking up a self- scheduling edge (Yucesan and Schruben)

EG -> PN Mapping 1. Split all self-scheduling edges (add conditions upstream of new vertex) 2. Add void edges (either conditional or timed but not both) to make graph “edge-bipartite” (expansion rules) 3. Timed edges become transitions and conditional edges become places

EG -> PN Mapping EG->PN not possible (Q>0) (S>0) ENTER {Q=Q+1} {S=0,Q=Q-1} {S=1} t a t s STARTLEAVE (CLK<100)

EG -> PN Mapping QUEUE START FINISH t t (Q) (S) s a {Q=Q+1} {Q=Q - 1, S=S - 1} {S=S+1}

EG -> PN Mapping QUEUE START FINISH t t (Q) (S) s a {Q=Q+1} {Q=Q - 1, S=S - 1} {S=S+1} QUEUE START FINISH t t (Q) (S) s a ? “Edge Bipartite”

EG -> PN Mapping QUEUE START FINISH t t (Q) (S) s a {Q=Q+1} {Q=Q - 1, S=S - 1} {S=S+1} QUEUE START FINISH t (Q) (S) s t a t s Timed Edges become Transitions t a ?

EG -> PN Mapping QUEUE START FINISH t t (Q) (S) s a {Q=Q+1} {Q=Q - 1, S=S - 1} {S=S+1} QUEUE START FINISH t (Q) (S) s t a t s Conditional Edges become PN places ??? t a ?

EG -> PN Mapping QUEUE START FINISH t t (Q) (S) s a {Q=Q+1} {Q=Q - 1, S=S - 1} {S=S+1} Q S ? QUEUE START FINISH t (Q) (S) s t a t s State changes on conditional edges determine labels t a ?

RunEnterStart1End1Start2 End2 tata t s1 t s2 ~ ~ ~ ~ ~ (i) COMMUNICATIONS BLOCKING: Edges Mapped from Petri Net Conditions to Start “Activities”: (i )= (R1&B&Q1) (ii) = (R2&Q2) (i) (ii)

RunEnterStart1End1Start2 End2 {R1=1, R2=1, B=4} {Q1--} {R1--, B--, Q1--} {R1++, Q2++} {R2--, Q2--} {R2++, B++} COMMUNICATIONS BLOCKING: State Changes R1,R2 = Number of idle resources Q1,Q2 = Number of waiting jobs B = Number of empty buffer spaces

RunEnterStart1End1Start2 End2 {R1=1, R2=1, B=4} {Q1--} {R1--, B--, Q1--} {R1++, Q2++} {R2--, Q2--} {R2++, B++} tata t s1 t s2 ~ ~ ~ ~ ~ (R2&Q2) (R1&B&Q1) (R2&Q2) (R1&B&Q1) COMMUNICATIONS BLOCKING: Final EGM Model R1,R2 = Number of idle resources Q1,Q2 = Number of waiting jobs B = Number of empty buffer spaces

Using Activity Scanning to Develop Process Models “Color” tokens that represent Transient Entities - - track these tokens’ paths. Parse Activities into “SEIZE”, “DELAY” and “RELEASE” Blocks. SEIZE DELAY RELEASE Idle Resources Queue

Process -> EG Mapping Process World View: Automated SLAM to Event Graphs (Woodward and Mackulak, ASU) Resource deadlock detection SIMAN to Event Graphs (Barton and Gonzalez, PSU) Premature run termination