Department of EECS University of California, Berkeley EECS 105 Fall 2003, Lecture 24 Lecture 24: Examples of Multistage Amps Prof. Niknejad

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Review: Frequency Resp of Multistage Amplifiers We have a systematic technique to study amplifier performance (derive transfer function, study poles/zeros/Bode pltos). In most cases, the systematic approach is too cumbersome. We have a good qualitative understanding of circuit performance (e.g., CS suffers from Miller effect, CD andd CG are wideband stages …) Open Circuit Time Constants: Analytical technique is capable of estimating only the dominant (lowest) pole …for a restricted class of amplifiers.

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley The Special Case The transfer function can have no zeroes and must have a dominant pole  1 <<  2,  3, …,  n Factor denominator:

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Approximating the Transfer Function Multiply out denominator: Since  1 <<  2,  3, …,  n 

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley How to Find b 1 ? See P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits (EE 140) for derivation Result: b 1 is the sum of open-circuit time constants  i which can be found by considering each capacitor C i in the amplifier separately and finding its Thévenin resistance R Ti   i = R Ti C i

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Finding the Thévenin Resistance 1.Open-circuit all capacitors (i.e.; remove them) 2.For capacitor C i, find the resistance R Ti across its terminals with all independent sources removed (voltages shorted, currents opened) … might need to apply a test voltage and find the current in some cases. Insight for design: the bandwidth of the amplifier will be limited by the capacitor that contributes the largest  i = R Ti C i  not necessarily the largest C i

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Complete Amplifier Schematic Goals: g m1 = 1 mS, R out =10 M 

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Device Sizes M 1 : select (W/L) 1 = 200/2 to meet specified g m1 = 1 mS  find V BIAS = 1.2 V Cascode current supply devices: select V SG = 1.5 V (W/L) 4 = (W/L) 4B = (W/L) 3 = (W/L) 3B = 64/2 M 2 : select (W/L) 2 = 50/2 to meet specified R out =10 M   find V GS2 = 1.4 V Match M 2 with diode-connected device M 2B. Assuming perfect matching and zero input voltage, what is V OUT ?

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Output (Voltage) Swing Maximum V OUT Minimum V OUT

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Port Model Find output resistance R out n = (1/20) V -1, n = (1/50) V -1 at L = 2  m  r on = (100  A / 20 V -1 ) -1 = 200 k , r op = 500 k 

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Stage Amplifier Topology Direct DC connection: use NMOS then PMOS

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Current Supply Design Assume that the reference is a “sink” set by a resistor Must mirror the reference current and generate a sink for i SUP 2

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Use Basic Current Supplies

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Complete Amplifier Topology What’s missing? The device dimensions and the bias voltage and reference resistor

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Multi-Stage Voltage Amplifier

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Cutting Through the Complexity Two Approaches: 1.Eliminate “background” transistors to reduce clutter 2. Identify the “signal path” between the input and output

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley First Approach: Find I & V Sources

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley What’s Left? Voltage at base of Q 2 is set by totem pole

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Second Approach: Find Signal Path

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Identifying the Stages First stage (or two stages): CS/CB cascode Second stage (or two stages): CD/CC voltage buffer Why does this make sense for a voltage amplifier?

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Find Key Two-Port Parameters Output resistance of cascode:

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Two-Port Parameters (Cont.)

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Output Resistance and Voltage Gain Source resistance of the CC stage is the output resistanceof the CD stage (small) Open-circuit voltage gain A v (last two stages have nearly unity gain):

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley DC Bias

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley DC Bias (Cont.) Simplifying assumption: Cascode current supply and totem pole: diode connected devices set both source-gate and source-drain voltages select input bias voltage such that I D1 = I D9 devices M 1, Q 2, M 6, and M 7 must have same |V DS | or V CE as M 9, Q 2B, M 6B, and M 7B (2 nd order effect)  sometimes called “replica biasing”

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Output Swing: V OUT,MIN Minimum output voltage: M 10, M 3, and Q 2 are “suspects” M 10 goes into triode when V OUT = 0.5 V M 3 goes into triode when V SD3 = 0.5 V  V OUT = 0.5 V – 0.7 V = -0.2 V Q 2 goes into saturation when V CE2 = 0.1 V or V BC2 = 0.6 V V OUT = V B2 – V BC2 + V SG3 – V BE4 = 2 V – 0.6 V V – 0.7 V V OUT = 2.2 V

EECS 105 Fall 2003, Lecture 24Prof. A. Niknejad Department of EECS University of California, Berkeley Output Swing: V OUT,MAX Maximum output voltage: Q 4, M 5, and M 6 are “suspects” Q 4 goes into saturation when V CE4 = 0.1 V  V OUT = 4. 9 V M 5 goes triode when V SD5 = 0.5 V  V OUT = 3.8 V M 6 goes triode when V SD6 = 0.5 V  V OUT = V S6 – 0.5 V + V SG3 – V BE4 = 3.5 – – 0.7 V = 3.8 V