Decoders and Encoders Discussion D4.2. Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders.

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Presentation transcript:

Decoders and Encoders Discussion D4.2

Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders

Decoders

3-to-8 Decoder Behavior input [2:0] A ; wire [2:0] A ; output [0:7] Y ; reg [0:7] Y ; for(i = 0; i <= 7; i = i+1) if(A == i) Y[i] = 1; else Y[i] = 0;

3-to-8 Decoder module decode38 ( A, Y ); input [2:0] A ; wire [2:0] A ; output [0:7] Y ; reg [0:7] Y ; integer i; for(i = 0; i <= 7; i = i+1) if(A == i) Y[i] = 1; else Y[i] = 0; endmodule decode38.v

3-to-8 Decoder

TTL Decoders GND Vcc1G 1A 1B 1Y0 1Y1 1Y2 1Y3 2G 2A 2B 2Y0 2Y1 2Y2 2Y3 74LS139 Y0 Y1 Y2 Y3BA G 1 X X Dual 2-4 Decoder

TTL Decoders GND VccA B C G1 Y7 Y0 Y1 Y2 Y3 Y4 Y5 Y6 !G2A !G2B 74LS138 ABC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 G1 G2 G2 = G2A # G2B X = don't care X 1 X X X X X X X to-8 Decoder

Decoder Networks

4-input tree decoder

8-input Coincident Decoder

Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders

Binary encoders

Encoders A B I0 I1 I2 I3 4-to-2 Encoder I0 I1 I2 I3 B A

Encoders I0 I1 I2 I3 B A Assume only 1 input can be high at any time. A = I1 + I3 B = I2 + I3 I1 I2 I3 I0 B = I2 + I3 A = I1 + I3

8-to-3 Encoder I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0 Y2 = I7 + I6 + I5 + I4 Y1 = I7 + I6 + I3 + I2 Y0 = I7 + I5 + I3 + I1

Uses of binary encoders

Decoders and Encoders Binary Decoders Binary Encoders Priority Encoders

Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 Y 2 Y 1 Y 0

Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X Y 2 = L 7 + L 6 + L 5 + L 4 L 7 = I 7 L 6 = I 7 'I 6 L 5 = I 7 'I 6 'I 5 L 4 = I 7 'I 6 'I 5 'I 4 I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 Y 2 Y 1 Y 0

Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X Y 1 = L 7 + L 6 + L 3 + L 2 I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 Y 2 Y 1 Y 0 L 7 = I 7 L 6 = I 7 'I 6 L 3 = I 7 'I 6 'I 5 'I 4 'I 3 L 2 = I 7 'I 6 'I 5 'I 4 'I 3 'I 2

Priority Encoder X X X X X X X X X X X X X X X X X X X X X X X X X X X X I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 Y 2 Y 1 Y 0 Y 0 = L 7 + L 5 + L 3 + L 1 L 7 = I 7 L 5 = I 7 'I 6 'I 5 L 3 = I 7 'I 6 'I 5 'I 4 'I 3 L 1 = I 7 'I 6 'I 5 'I 4 'I 3 'I 2 'I 1

TTL Priority Encoder GND Vcc A2 A1 E1 E0 GS 0 A0 74LS148 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X EI A2 A1 A0 GS EO Priority Encoder

68000 Interrupt Logic Peripheral Encoder Decoder IP0 IP1 IP2 A0 A1 A2 IRQA Data Bus IRQ

entity pencoder is port ( x: in STD_LOGIC_VECTOR (7 downto 0); E: in STD_LOGIC; y: out STD_LOGIC_VECTOR (2 downto 0); A: out STD_LOGIC ); end pencoder; 8-to-3 Priority Encoder

architecture pencoder_arch of pencoder is begin pe: process(x,E) variable k: integer; begin y <= "000"; A <= '0'; if E = '1' then for j in 0 to 7 loop if x(j) = '1' then y <= conv_std_logic_vector(j,3); A <= '1'; end if; end loop; end if; end process pe; end pencoder_arch;