Prof. Muhammad Saeed III

1/27/2015Computer Architecture & Assembly Language2 Assembly Language Instructions

1/27/2015Computer Architecture & Assembly Language3 MOV reg, reg MOV mem, reg MOV reg, mem MOV mem, imm MOV reg, imm Language Instructions †MOV MOVZX reg32, reg/mem8 MOVZX reg32, reg/mem16 MOVZX reg16, reg/mem8 †MOVZX MOVSX reg32, reg/mem8 MOVSX reg32, reg/mem16 MOVSX reg16, reg/mem8 †MOVSX

1/27/2015Computer Architecture & Assembly Language4 †XCHG XCHG reg, reg XCHG reg, mem XCHG mem, reg INC reg/mem DEC reg/mem †INC, DEC The Overflow, Sign, Zero, Auxiliary Carry, and Parity flags are changed according to the value of the destination operand. †ADD, SUB ADD dest, source The Carry, Zero, Sign, Overflow, Auxiliary Carry, and Parity flags are changed according to the value that is placed in the destination operand. SUB dest, source NEG reg NEG mem †NEG The Carry, Zero, Sign, Overflow, Auxiliary Carry, and Parity flags are changed according to the value that is placed in the destination operand. Language Instructions

The PUSH instruction first decrements ESP and then copies a source operand into the stack. A 16-bit operand causes ESP to be decremented by 2. A 32-bit operand causes ESP to be decremented by 4. †PUSH †POP PUSH reg/mem16 PUSH reg/mem32 PUSH imm32 The POP instruction first copies the contents of the stack element pointed to by ESP into a 16- or 32-bit destination operand and then increments ESP. If the operand is 16 bits, ESP is incremented by 2; if the operand is 32 bits, ESP is incremented by 4 POP reg/mem16 POP reg/mem32 Language Instructions

†PUSHFD and POPFD The PUSHFD instruction pushes the 32-bit EFLAGS register on the stack, and POPFD pops the stack into EFLAGS. †PUSHAD and POPAD The PUSHAD instruction pushes all of the 32-bit general-purpose registers on the stack in the given order: EAX, ECX, EDX, EBX, ESP, EBP, ESI, and EDI. The POPAD instruction pops the same registers off the stack in reverse order. †PUSHA and POPA PUSHA instruction, pushes the 16-bit general-purpose registers (AX, CX, DX, BX, SP, BP, SI, DI) on the stack in the order listed. The POPA instruction pops the same registers in reverse Language Instructions

†LOOP The LOOP instruction assumes that the ECX (or CX) register contains the loop count. When the loop instruction is executed, the CX register is decremented and the control jumps to the target label, until the CX register value reaches zero. Language Instructions †Unconditional Jump Jmp label1

Language Instructions InstructionDescriptionFlags tested JE/JZJump Equal or Jump ZeroZF JNE/JNZJump not Equal or Jump Not ZeroZF JG/JNLEJump Greater or Jump Not Less/Equal OF, SF, ZF JGE/JNLJump Greater or Jump Not LessOF, SF JL/JNGEJump Less or Jump Not Greater/Equal OF, SF JLE/JNGJump Less/Equal or Jump Not Greater OF, SF, ZF †Conditional Jumps Following are the conditional jump instructions used on signed data

Language Instructions †Conditional Jumps Following are the conditional jump instructions used on unsigned data InstructionDescriptionFlags tested JE/JZJump Equal or Jump ZeroZF JNE/JNZJump not Equal or Jump Not ZeroZF JA/JNBEJump Above or Jump Not Below/EqualCF, ZF JAE/JNBJump Above/Equal or Jump Not BelowCF JB/JNAEJump Below or Jump Not Above/EqualCF JBE/JNAJump Below/Equal or Jump Not AboveAF, CF

Language Instructions †Conditional Jumps The following conditional jump instructions have special uses and check the value of flags InstructionDescriptionFlags tested JXCZJump if CX is Zeronone JCJump If CarryCF JNCJump If No CarryCF JOJump If OverflowOF JNOJump If No OverflowOF JP/JPEJump Parity or Jump Parity EvenPF JNP/JPOJump No Parity or Jump Parity OddPF JSJump Sign (negative value)SF JNSJump No Sign (positive value)SF

†AND AND reg,reg AND reg,mem AND reg,imm AND mem,reg AND mem,imm The AND instruction performs a boolean (bitwise) AND operation between each pair of matching bits in two operands and places the result in the destination operand †OR The OR instruction performs a boolean OR operation between each pair of matching bits in two operands and places the result in the destination operand OR reg,reg OR reg,mem OR reg,imm OR mem,reg OR mem,imm Language Instructions

†XOR The XOR instruction performs a boolean exclusive-OR operation between each pair of matching bits in two operands and stores the result in the destination operand OR reg,reg OR reg,mem OR reg,imm OR mem,reg OR mem,imm †NOT The NOT instruction toggles (inverts) all bits in an operand NOT reg NOT mem Language Instructions

†TEST Language Instructions The TEST instruction performs an implied AND operation between each pair of matching bits in two operands and sets the Sign, Zero, and Parity flags based on the value assigned to the destination operand. The only difference between TEST and AND is that TEST does not modify the destination operand. The TEST instruction always clears the Overflow and Carry flags. It modifies the Sign, Zero, and Parity flags in the same way as the AND instruction.

Language Instructions †CMP In x86 assembly language we use the CMP instruction to compare integers. Character codes are also integers, so they work with CMP as well. The CMP (compare) instruction performs an implied subtraction of a source operand from a destination operand. Neither operand is modified. CMP uses the same operand combinations as the AND instruction.

Language Instructions †Directive †Instruction †Procedure  myproc PROC …… ret myproc endp (call myproc) †Macro  myMacro MACRO …….. endm(myMacro)

†PTR Operator PTR operator overrides the declared size of an operand to access the operand using a size attribute that is different from the one assumed by the assembler. MOV eax, WORD PTR [var] †LENGTHOF Operator The LENGTHOF operator counts the number of elements in an array Language Instructions Var1 WORD 20 DUP(0) Var2DWORD 20 DUP(0) LENGTHOF var1 †SIZEOF Operator Var1 WORD 20 DUP(0) Var2DWORD 20 DUP(0) SIZEOF var1 The SIZEOF operator counts the number of bytes in an array †($ - array) Array BYTE “WELCOME”, 0dh, 0ah Size WORD( $-Array )

†LABEL Directive The LABEL directive gives a size attribute without allocating any storage Language Instructions.DATA val16 LABEL WORD val32 DWORD h.CODE mov ax,val16 mov dx,[val16+2].DATA LongValue LABEL DWORD val1 WORD 5678h val2 WORD 1234h.CODE mov eax,LongValue

Language Instructions †Indexed Operand An indexed operand adds a constant to a register to generate an effective address.DATA array BYTE 10h, 20h, 30h.CODE mov esi,0 mov al,array[esi] †Scale Factors in Indexed Operand.DATA ArrayDWORD 100h, 200h, 300h, 400h.CODE mov esi, 3 * TYPE array mov eax,array[esi]

Language Instructions

1/27/2015Computer Architecture & Assembly Language21 Program 1 st Program.586.MODEL flat, stdcall option casemap :none Include D:\msaeed\academic\assemblylanguage\masm32\include\windows.inc Include D:\msaeed\academic\assemblylanguage\masm32\include\kernel32.inc Include D:\msaeed\academic\assemblylanguage\masm32\include\user32.inc Includelib D:\msaeed\academic\assemblylanguage\masm32\lib\kernel32.lib Includelib D:\msaeed\academic\assemblylanguage\masm32\lib\user32.lib.DATA WindowTitle BYTE “Greetings",0 Message BYTE “Hello, World",0.CODE main: invoke MessageBox, NULL, ADDR Message, ADDR WindowTitle, MB_OK invoke ExitProcess, eax end main

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