Elettronica T AA 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Interconnect Interconnect and Communication.

Slides:

Advertisements

Similar presentations

Digital Integrated Circuits© Prentice Hall 1995 Combinational Logic COMBINATIONAL LOGIC.

Advertisements

Digital Integrated Circuits© Prentice Hall 1995 Low Power Design Low Power Design in CMOS.

EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 SRAM & DRAM.

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Inverter CMOS INVERTER.

Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.

ECE 124a/256c VLSI RC(L) Interconnect Models Forrest Brewer Wayne Burleson, Atul Maheshwari.

Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.

Adapted from Digital Integrated Circuits, 2nd Ed. 1 IC Layout.

Institute of Computer Systems / TKT ASIC Design II / O. Vainio  Lectures by Olli Vainio  5 credits  Prerequisites (recommended): TKT-1212.

© Digital Integrated Circuits 2nd Inverter Impact of Interconnect  Interconnection  Fundamental limitation of Digital Technology at all scales  Classes.

04/11/02EECS 3121 Lecture 26: Interconnect Modeling, continued EECS 312 Reading: 8.2.2, (text) HW 8 is due now!

SoC Interconnect Modeling Venkata Krishna N. Dhulipala 11/20/2008.

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 14: Interconnects Prof. Sherief Reda Division of Engineering, Brown University.

EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Wire Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)

Lecture #25a OUTLINE Interconnect modeling

Digital Integrated Circuits© Prentice Hall 1995 Introduction Jan M. Rabaey Digital Integrated Circuits A Design Perspective.

Combinational MOS Logic Circuit

Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 9.1 EE4800 CMOS Digital IC Design & Analysis Lecture 9 Interconnect Zhuo Feng.

Elettronica D. AA Digital Integrated Circuits© Prentice Hall 1995 Manufacturing Process CMOS Manufacturing Process.

Circuit Characterization Feb 4, Basic Device Equations (p.51)  Cutoff region: V gs  V t  I ds = 0  Linear/non-saturation region: 0

Noise and Delay Uncertainty Studies for Coupled RC Interconnects Andrew B. Kahng, Sudhakar Muddu † and Devendra Vidhani ‡ UCLA Computer Science Department,

Cascading CMOS gates. Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Goal l Designing for minimum propagation.

EGRE 427 Advanced Digital Design Figures from Application-Specific Integrated Circuits, Michael John Sebastian Smith, Addison Wesley, 1997 Chapter 3 ASIC.

VLSI System Design Pradondet Nilagupta Department of Computer Engineering Kasetsart University.

ECE 424 – Introduction to VLSI Design

A Methodology for Interconnect Dimension Determination By: Jeff Cobb Rajesh Garg Sunil P Khatri Department of Electrical and Computer Engineering, Texas.

DSM Design and Verification Flow

EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.

Crosstalk Analysis in UDSM technologies

Written By: Kris Tiri and Ingrid Verbauwhede Presented By: William Whitehouse.

Elmore Delay, Logical Effort

Digital Integrated Circuits© Prentice Hall 1995 Interconnect COPING WITH INTERCONNECT.

EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Interconnect Jan M. Rabaey Anantha Chandrakasan Borivoje.

EE415 VLSI Design 1 The Wire [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE141 © Digital Integrated Circuits 2nd Wires 1 Digital Integrated Circuits A Design Perspective The Wire Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic.

© Digital Integrated Circuits 2nd Interconnect ECE 558/658 : Lecture 20 Interconnect Design (Chapter 9) Clock distribution (Chapter ) Atul Maheshwari.

Digital Integrated Circuits© Prentice Hall 1995 Devices Jan M. Rabaey The Devices.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire and via structures. n Wire parasitics. n Transistor parasitics.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Circuit design for FPGAs n Static CMOS gate vs. LUT n LE output drivers n Interconnect.

VLSI Design Lecture 3: Parasitics of CMOS Wires Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture.

Session 5: Projects 1. Physical Limits of Technology Scaling : 2 SCALING AND EFFICIENCY.

INTERCONNECT MODELING M.Arvind 2nd M.E Microelectronics

1 Interconnect/Via. 2 Delay of Devices and Interconnect.

EE 4271 VLSI Design, Fall 2013 Static Timing Analysis and Gate Sizing Optimization.

VLSI INTERCONNECTS IN VLSI DESIGN - PROF. RAKESH K. JHA

Interconnect/Via.

Chapter 4: Secs ; Chapter 5: pp

Modern VLSI Design 3e: Chapter 3 Copyright  1998, 2002 Prentice Hall PTR Topics n Wire delay. n Buffer insertion. n Crosstalk. n Inductive interconnect.

7. Direct Current circuits. 11 Find the currents, which flow in all the wires of the circuit in this figure 12  9 V 6 V b a cd 18 

CSE477 L27 System Interconnect.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 27: System Level Interconnect Mary Jane Irwin (

Objectives: 1. Define and calculate the capacitance of a capacitor. 2. Describe the factors affecting the capacitance of the capacitor. 3. Calculate the.

Wires & wire delay Lecture 9 Tuesday September 27, 2016.

Crosstalk If both a wire and its neighbor are switching at the same time, the direction of the switching affects the amount of charge to be delivered and.

EE141 Chapter 4 The Wire March 20, 2003.

Chapter 4 Interconnect.

מיחזור במערכת החינוך.

Chapter 3 Inductance and Capacitance

Copyright © 2008 Pearson Prentice Hall Inc.

Copyright © 2008 Pearson Prentice Hall Inc.

Copyright © 2008 Pearson Prentice Hall Inc.

Copyright © 2008 Pearson Prentice Hall Inc.

COPING WITH INTERCONNECT

Reading (Rabaey et al.): Sections 3.5, 5.6

BETONLINEBETONLINE A·+A·+

Copyright © 2008 Pearson Prentice Hall Inc.

Copyright © 2008 Pearson Prentice Hall Inc.

THE INTERCONNECT.

Presentation transcript:

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Interconnect and Communication

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Impact of Interconnect Parasitics

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Modern Interconnect

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Nature of Interconnect Global Interconnect S Local = S Technology S Global = S Die Source: Intel

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Nature of Interconnect

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Capacitive interconnect

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Capacitance: The Parallel Plate Model C int =є ox /t ox WL

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Typical Wiring Capacitance Values

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Fringing Capacitance

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Fringing Capacitance: Values

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Interwire Capacitance

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Interwire Capacitance

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Impact of Interwire Capacitance

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Capacitive Crosstalk

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect How to Battle Capacitive Crosstalk

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Resistive interconnect

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Wire Resistance

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Interconnect Resistance

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Dealing with Resistance

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect RC-Delay

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect RC-Models

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Reducing RC-delay Repeater

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect The Elmore Delay R1 R2 R3 v in v out C1C2C3  elmore =C3(R1+R2+R3) + C2(R1+R2) + C1(R1)

Elettronica T AA Digital Integrated Circuits © Prentice Hall 2003 Interconnect Penfield-Rubinstein-Horowitz R1 R2 R3 v in v out C1C2C3  elmore =C3(R1+R2+R3) + C5(R1+R2) + C2(R1+R2) + C4(R1) + C1(R1) R4 R5 C4 C5