Cascading CMOS gates. Elettronica T A.A. 2010-2011 Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Goal l Designing for minimum propagation.

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Presentation transcript:

Cascading CMOS gates

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Goal l Designing for minimum propagation delay: Fixed number of stages Optimum number of stages

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Example 1:Two cascaded inverters S=W/L CL/Ci=  Ip: Cp= Cin(Inv2) Inv2 Inv1 Cp= u Ci SSuSuS uS Cp CL ViVpVo

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Transistor sizing two cascading stages: minimize propagation delay: Vi Vp (u) Vo Ci Cp CL I B

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Example Two stages are faster than one if:

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Sizing Logic Paths for Speed l Frequently, input capacitance of a logic path is constrained l Logic also has to drive some capacitance l Example: ALU load in an Intel’s microprocessor is 0.5pF l How do we size the ALU datapath to achieve maximum speed? l We have already solved this for the inverter chain – can we generalize it for any type of logic?

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Delay in a Logic Gate Gate delay: d = h + p effort delay intrinsic delay Effort delay: h = g f logical effort effective fanout = C out /C in Logical effort is a function of topology, independent of sizing Effective fanout (electrical effort) is a function of load/gate size

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Optimum number of stages: buffer Why a buffer - long interconnection wires - chip interfaces

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Chip interface: an example Pentium (7 buffer) L = ( ) nH Cp = ( ) pF Co = ( ) pF PADPIN CoCp L

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Long interconnection wires

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Single interconnection capacitance

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Total interconnection capacitance

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Example: 2 inverter stages F Too large !

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Multiple stage Buffer VGVG C1C2 C N-1 CL Vi V1 V2Vo N u u2u2 u N-1

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Cascading CMOS inverters Minimizing tp:

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Propagation delay vs sizing factor u

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Example CMOS 1  m; Ci=10fF; tp 0.2ns CL=20pF X= stages tp 4ns Stage Wn(  m) Wp(  m)

Elettronica T A.A Digital Integrated Circuits © Prentice Hall 2003 Cascading CMOS Tri-State CMOS Buffer