Chip Planning 1

Introduction Chip Planning:  Deals with large modules with −known areas −fixed/changeable shapes −(possibly fixed locations for some modules)  If modules not defined clearly  physical hierarchy Examples:  IP Cores  Caches  Embedded Memories  … 2

Chip Planning Steps Steps: 1.Floorplanning: −Determines location and shapes −Based on area, aspect ratio −Optimizes −Area −Interconnects −Timing 2.Pin assignment 3.Power planning 3

Chip Planning Steps Steps: 1.Floorplanning: 2.Pin assignment: −Assigns signal nets to block pins −Finds locations of IO pads 3.Power planning 4

Chip Planning Steps Steps: 1.Floorplanning: 2.Pin assignment: 3.Power planning: −Builds power supply network −Should supply P&G to all circuits 5

6 Chip Planning GND VDD Module e I/O Pads Block Pins Block a Block b Block d Block e Floorplan Module d Module c Module b Module a Chip Planning Block c Supply Network © 2011 Springer Verlag Connections between blocks: through internal pins (not shown)

Pentium-4 Floorplan 7

Floorplanning Module  becomes a rectangular block after it is assigned dimensions or a shape −Can be rectilinear Blocks:  Hard: −Dimensions: fixed  Soft: −Area: fixed −Aspect ratio: changeable (discrete or continuous) 8

Floorplan Floorplan with soft blocks: :  Determines positions and shapes for blocks Floorplanning with hard blocks:  Pre-existing IP blocks: special case −but requires special computational techniques Hierarchical:  Usually recursive top-down  Focus on one level at a time 9

10 Hierarchical Floorplan A D E B C

Floorplan Area Optimization: Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed A A A B B C C

12 Example Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed

13 Example Solution: Aspect ratios Block A with w = 2, h = 2; Block B with w = 2, h = 1; Block C with w = 1, h = 3 This floorplan has a global bounding box with minimum possible area (9 square units). Given: Three blocks with the following potential widths and heights Block A: w = 1, h = 4 or w = 4, h = 1 or w = 2, h = 2 Block B: w = 1, h = 2 or w = 2, h = 1 Block C: w = 1, h = 3 or w = 3, h = 1 Task: Floorplan with minimum total area enclosed

14 Floorplanning Problem Inputs:  n Blocks with areas A 1,..., A n  Bounds r i and s i on the aspect ratio of block B i Outputs:  Coordinates (x i, y i ),  width w i and height h i for each block such that: h i.w i = A i and r i  h i /w i  s i Objectives:  Area  ….

Objective Functions Objectives:  Area of global bounding box: −Area of chip (at top level) −  higher performance −  better manufacturing cost  Shape of global bounding box: −Aspect ratio: Close to target shape −E.g., Closer to square (AR = 1) 15

Objective Functions Objectives:  Total wirelength: −Short wires −  faster −  less power consumption −  better routability −  less area (  less cost) 16

17 Wirelength Estimation In floorplanning:  Exact wirelength of each net: not known −Routing not done −Even pin locations may not be known Estimations:  Center-to-center Euclidean estimation (MST for multi-term’l)  Half-perimeter estimation −Relatively accurate for medium-sized and small blocks −Rapid evaluation

18 Deadspace Minimizing area = minimizing deadspace. Deadspace percentage:  ((A -  i A i ) / A)  100% Deadspace

19 Bounds on Aspect Ratios If no bound on the aspect ratios  No deadspace In practice: r i  h i /w i  s i for each i

Objectives Fixed outline floorplan:  Size and dimensions are known (constraint rather than objective) 20

21 Hierarchical Floorplan Hierarchical floorplan of order k:  If it can be obtained by recursively partitioning a rectangle into at most k parts.

22 A Floorplan with Slicing Tree FGHIDEA 8 BC A B C DE FG HI

23 Slicing Floorplans Two possible corresponding slicing trees b d a e c f a cb d e f H V H H V H V H d c e f H V ba © 2011 Springer Verlag Slicing floorplan

24 Slicing Floorplans Polish expression b d a e c f a cb d e f H V H H V B+C  ADEF  ++  Bottom up: V   and H  +  Length 2n-1 (n = Number of leaves of the slicing tree)

25 Non-Slicing Floorplans Non-slicing floorplans (wheels) b d a e c a b c d e © 2011 Springer Verlag

26 Hierarchical Floorplans Floorplan tree: Tree that represents a hierarchical floorplan a b c d e f g h i H H H H V W h i c d e f g a b H H Horizontal division (objects to the top and bottom) H V Vertical division (objects to the left and right) H W Wheel (4 objects cycled around a center object)

27 Linear Programming Approach “An Analytical Approach to Floorplan Design and Optimization”, Sutanthavibul, Shragowitz and Rosen, IEEE Transaction on CAD, 10: , June “An Analytical Approach to Floorplan Design and Optimization”, Sutanthavibul, Shragowitz and Rosen, IEEE Transaction on CAD, 10: , June 1991.

28 Mixed Integer Linear Program A mathematical program such that:  The objective is a linear function.  All constraints are linear functions.  Some variables are real numbers and some are integers, i.e., “mixed integer”. It is almost like a linear program, except that some variables are integers.

29 Problem Formulation Minimize the packing area:  Area is non-linear   Assume that one dimension W is fixed.  Minimize the other dimension Y. Need to have constraints - so that blocks do not overlap. Associate each block B i with 4 variables:  x i and y i : coordinates of its lower left corner.  w i and h i : width and height. W Y

30 Non-overlapping Constraints For two non-overlapping blocks B i and B j, at least one of the following four linear constraints must be satisfied: BiBi BjBj (x i, y i ) (x j, y j ) hihi hjhj wiwi wjwj

31 Integer Variables Use integer (0 or 1) variables x ij and y ij : x ij =0 and y ij =0 if (1) is true. x ij =0 and y ij =1 if (2) is true. x ij =1 and y ij =0 if (3) is true. x ij =1 and y ij =1 if (4) is true. Let W and H be upper bounds on the total width and height. Non-overlapping constraints:

32 Formulation Let W is known.

33 Solving Linear Program Linear Programming (LP) can be solved by classical optimization techniques in polynomial time. Mixed Integer LP (MILP) is NP-Complete.  The run time of the best known algorithm is exponential to the no. of variables and equations.  Groups the modules and processes each group successively. FSF, Free Software Foundation (2006). GLPK (GNU Linear Programming Kit).

34 Example  Desired aspect ratio: 1.  Four fixed modules: m1(4, 5), m2(3, 7), m3(6, 4), and m4(7, 7). −(w, h) −Rotation allowed.  coordinate variables (x1, x2, x3, x4, y1, y2, y3, y4)  upper bound of chip boundary: W =  w i = = 20 H =  h i = = 23

35 non-overlap constraints: x1 + w1 ≤ x2 + 20(x12 + y12) x1 - w2 ≥ x2 - 20(1 - x12 + y12) y1 + h1 ≤ y2 + 23(1 + x12 - y12) y1 - h2 ≥ y2 - 23(2 - x12 - y12) x1 + w1 ≤ x3 + 20(x13 + y13) x1 - w3 ≥ x3 - 20(1 - x13 + y13) y1 + h1 ≤ y3 + 23(1 + x13 - y13) y1 - h3 ≥ y3 - 23(2 - x13 - y13) ….