Mixed Logic Circuit Design Benjamin Suan Presentation for High-Speed and Low Power VLSI Course: 97.575 Instructor: Dr. Maitham Shams

Contents Introduction Discussion Project Proposal Background Information Discussion Logic style sample comparisons Mixed logic circuit design Project Proposal Project time-line

Introduction Mixed Logic Circuits Reason to Use Relatively new area of research Circuits composed of more than one logic type Reason to Use Each logic type has different advantages / disadvantages By implementing two logics, gain advantages of both

Current Trends Industry Trend Research Trend Lower power Higher speed Smaller area Research Trend Recent papers published in mixed logic design Papers focused on PTL / CMOS circuits

Background Standard CMOS Characteristics Most commonly used logic in VLSI design Ease of use, well developed synthesis methods High noise margins Low power consumption No static power dissipation Good current driving capabilities

Background cont’d Pass Transistor Logic Characteristics Widely used alternative to complementary CMOS Fewer transistors are required for a given function Reduced number of transistors means there is lower capacitance Dedicated buffers need to be inserted to boost driving strength

Logic Comparison M. Kontiala, M. Kuulusa and J. Nurmi, “Comparison of Static Logic Styles for Low-Voltage Design” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on , Volume: 3 , 2001

Logic Comparison cont’d

Full Adder Implementation

Propagation Delay Results

Power Dissipation Results

Power Delay Products

Discussion of Results SCMOS has the best characteristics for low voltage speed and power dissipation No real motivation to develop mixed circuits with these other types of logic

CMOS and PTL

CMOS and CPL Behavior Results from adder simulation CPL has lower power dissipation across all supply voltages CPL has lower delay time across all supply voltages

Mixed PTL/CMOS Logic PTL/CMOS logic circuits will be superior Better area, power and delay compared to conventional CMOS or PTL Low power, high performance design driven by PTL cell selection and synthesis technique to produce the mixed structure

Mixed PTL/CMOS Example Pass-transistor/CMOS Collaborated Logic: The Best Of Both Worlds Yamashita, S.; Yano, K.; Sasaki, Y.; Akita, Y.; Chikata, H.; Rikino, K.; Seki, K.; VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on , 12-14 Jun 1997 Page(s): 31 -32 Design assigned selector functions to PTL AND/OR logic functions mapped to CMOS

Design Example Design based on this Boolean equation: Out1 = B * A’ + C * A ( I’ * F’ + D’ ) * ( D + ( H + E’) * ( E + G )) Out2 = B’ + ( I’ + F’ + D’ ) * ( D + ( H + E’) * ( E + G )))’

Design Example cont’d

Design Example cont’d ii

Experimental Results

Experimental Results cont’d Benchmark simulations show the mixed circuits have better characteristics than pure PTL or CMOS 20% in area vs. CMOS 40% in power vs. CMOS Design flexibility ↑% of PTL, ↓ power but ↑ area

Design Project Plan Implement an algorithm in PTL For mixed logic design, implement MUX and XOR/XNOR type logic functions in PTL and the remaining functions in Static CMOS Compare and discuss power consumption and delay

Design Project Plan cont’d Schedule April 1 - 12 Logic Synthesis Technique / Background Research April 13 – 19 Design Phase / Schematic Capture April 20 – 30 Simulation / Project Presentation May 1 – 5 Report / Documentation

References Yamashita, S.; Yano, K.; Sasaki, Y.; Akita, Y.; Chikata, H.; Rikino, K.; Seki, K., “Pass-transistor/CMOS Collaborated Logic: The Best Of Both Worlds” VLSI Circuits, 1997. Digest of Technical Papers., 1997 Symposium on , 12-14 Jun 1997 Page(s): 31 -32 Geun Rae Cho; Chen, T., “On the impact of technology scaling on mixed PTL/static circuits” Computer Design: VLSI in Computers and Processors, 2002. Proceedings. 2002 IEEE International Conference on , 2002 Page(s): 322 -326 M. Kontiala, M. Kuulusa and J. Nurmi, “Comparison of Static Logic Styles for Low-Voltage Design” Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on , Volume: 3 , 2001 Geun Rae Cho; Chen, T.; “ Mixed. PTL/static logic synthesis using genetic algorithms for low-power applications” Quality Electronic Design, 2002. Proceedings. International Symposium on , 2002 Page(s): 458 -463 Congguang Yang; Ciesielski, M., “Synthesis for mixed CMOS/PTL logic” Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings , 2000 Page(s): 750 Yano, K.; Yamanaka, T.; Nishida, T.; Saitoh, M.; Shimohigashi, K.; Shimizu, A., “A 3.8 ns CMOS 16×16 multiplier using complementary pass transistor logic” Custom Integrated Circuits Conference, 1989., Proceedings of the IEEE 1989 , 15-18 May 1989 Page(s): 10.4/1 -10.4/4