1 Chapter 6 Functions of Combinational Logic

2 Figure 6--1 Logic symbol for a half-adder Adder

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4 Figure 6--2 Half-adder logic diagram.

5 Figure 6--3 Logic symbol for a full-adder

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7 Figure 6--4 Full-adder logic

8 Figure 6--5 Full-adder implemented with half-adders.

9 Figure 6--7 Block diagram of a basic 2-bit parallel adder using two full-adders.

10 Figure 6--9 A 4-bit parallel adder.

11 Figure Four-bit parallel adders.

12 Figure Examples of adder expansion.

13 Figure Two 74LS83A adders connected as an 8-bit parallel adder (pin numbers are in parentheses).

14 Figure A voting system using full-adders and parallel binary adders.

15 Figure Basic comparator operation. (Equality) Comparators

16 Figure Logic diagram for equality comparison of two 2-bit numbers

17 Figure : Example 6-5

18 Figure Logic symbol for a 4-bit comparator with inequality indication.

19 Figure 6—19 : Example 6-6

20 Figure Pin diagram and logic symbol for the 74HC85 4-bit magnitude comparator (pin numbers are in parentheses).

21 Figure An 8-bit magnitude comparator using two 74HC85s.

22 Figure Decoding logic for the binary code 1001 with an active-HIGH output. Decoders

23 Figure Decoding logic for producing a HIGH output when 1011 is on the inputs.

24 Figure Logic symbol for a 4-line-to-16-line (1-of-16) decoder.

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26 Figure The 74HC42 BCD-to-decimal decoder. BCD-to-Decimal Decoder

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28 Figure 6--29

29 Figure Logic symbol for a BCD-to-7-segment decoder/driver with active-LOW outputs. BCD-to-7-Segment Decoder

30 Figure Pin diagram and logic symbol for the 74LS47 BCD-to-7-segment decoder/driver.

31 Figure Examples of zero suppression using the 74LS47 BCD to 7-segment decoder/driver.

32 Figure Logic symbol for a decimal-to-BCD encoder. Encoders

33 Figure Basic logic diagram of a decimal-to-BCD encoder. A 0-digit input is not needed because the BCD outputs are all LOW when there are no HIGH inputs.

34 Figure Pin diagram and logic symbol for the 74HC147 decimal-to-BCD priority encoder (HPRI means highest value input has priority).

35 Figure Logic symbol for the 74F148 8-line-to-3-line encoder.

36 Figure A 16-line-to-4 line encoder using 74F148s and external logic.

37 Figure A simplified keyboard encoder.

38 Code Converter BCD-to-Binary Conversion

39 Figure Four-bit binary-to-Gray conversion logic.

40 Figure Four-bit Gray-to-binary conversion logic

41 Figure : Example 6-13

42 Figure Logic symbol for a 1-of-4 data selector/multiplexer. Multiplexers (Data Selectors)

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44 Figure Logic diagram for a 4-input multiplexer.

45 Figure 6--44

46 Figure Pin diagram and logic symbol for the 74HC157A quadruple 2-input data selector/multiplexer.

47 Figure Pin diagram and logic symbol for the 74LS151 8-input data selector/multiplexer.

48 Figure A 16-input multiplexer.

49 Figure Simplified 7-segment display multiplexing logic.

50 Figure A 1-line-to-4-line demultiplexer. Demultiplexers

51 Figure 6--52

52 Figure The 74HC154 decoder used as a demultiplexer.

53 Figure Parity Generators/Checkers

54 Figure The 74LS280 9-bit parity generator/checker.

55 Figure Typical configuration for conventional PLD programming. Programmable Logic

56 Figure Flow chart of an SPLD conventional programming sequence.

57 Figure Typical configuration for in-system programming of a PLD.