Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France LHCb upgrade meeting Tests tools Status for Analog and Digital parts  Tools to test Analog part  Tools to test A3PE FPGA (SSO & SSI)  Conclusion : next steps Caceres Thierry Duarte Olivier

Olivier Duarte / Thierry Caceres Tools to test Analog part LHCb upgrade meeting 2 SPY_FIFO ANALOG_PULSE_ FIFO ClkUSB PATTERN_ FIFO setup_ register[8 ] setup_ register[9 ] setup_register[9] {Add 0x1C} 96 A3PE RDWR RDWR RDWR (96 x 512) (8 x 512) (96 x 512) {Add 0x1F} {Add 0x06} Buffer_FIFOs (12x8) USB wr 0 1 USB_data 8 8 USB data x 12bits 96 8 USB_data bit ADC data from Analog Mezzanine (x8) Analog Pulse ( 1 per ADC Channels) Clk 40 Mhz Wr : USB Rd : USB or 40 Mhz Wr : USB or 40 Mhz Rd : USB Wr : USB Rd : USB or 40 Mhz ADC emulationSPY data Trigger for Analog  FIFO pattern  Generate digital signals  Check FPGA computations  SPY FIFO storage of processing results  ANALOG PULSE FIFO generate trigger of analog pulses February 17th 2011

Olivier Duarte / Thierry Caceres Tools to test A3PE FPGA (SSO & SSI) LHCb upgrade meeting 3 Idea : RAM pattern to test the A3PE IOs functioning by exchanging data between the 2 FPGA (SSO and SSI)  USB Rd / Wr the RAM (To_AX and From_AX).  Start / Stop and latency (implemented !) Sequence:  To_AX _RAM Rd/Wr by USB  Start commande  Loop on to AX_RAM until stop command  Programmable latency to capture data from To_AX_RAM to FROM_AX_RAM February 17th 2011 From_AX_ RAM A3PE CLK_1 ClkUSB To_AX_RAM setup_register[10 ] 32 setup_register[11 ] RegUSB 32 _q3 AX500 setup_register[11 ] 32 BUSLSB AXTOA3PE BUSMSB AXTOA3PE 32 _q2 _q_q1 {Add 0x1D} (32 x 512) {Add 0x1E} (32 x 512 ) Rd Wr Buffer_FIFOs USB_data 32 8 USB_data 8 32 USB_data 8 32 Wr Rd Wr : USB Rd : USB or Clk_1 Wr : USB or Clk_1 Rd : USB From Delay Chip Ctrl. Wr / Rd pattern

Olivier Duarte / Thierry Caceres Start Stop Latency sequence LHCb upgrade meeting 4 February 17th 2011 Tunable latency START SEQ LATENCY Rd To AX RAM 512 words writed Wr From AX RAM STOP SEQ START / STOP / LATENCY SEQUENCE From_AX_ RAM A3PE CLK_1 ClkUSB To_AX_RAM setup_register[10 ] 32 setup_register[11 ] RegUSB 32 _q3 AX500 setup_register[11 ] 32 BUSLSB AXTOA3PE BUSMSB AXTOA3PE 32 _q2 _q_q1 {Add 0x1D} (32 x 512) {Add 0x1E} (32 x 512 ) Rd Wr Buffer_FIFOs USB_data 32 8 USB_data 8 32 USB_data 8 32 Wr Rd Wr : USB Rd : USB or Clk_1 Wr : USB or Clk_1 Rd : USB From Delay Chip Ctrl. Wr / Rd pattern Status:  Firmware implemented  Cycle ok  To debug :  Rd / Wr RAM  FPGA Download  Started tests of the third board Loop

Olivier Duarte / Thierry Caceres Conclusion LHCb upgrade meeting 5  Digital electronic is ok, several adjustment have been done.  Last adjustment of the tools to test A3PE FPGA (SSO & SSI).  Started tests of third mother digital board.  Should we considered a 8 channels prototype FEB for the beginning of 2013 with GBT (availability of the first GBT samples) ?  Common tests in Barcelona ? February 17th 2011

Olivier Duarte / Thierry Caceres LHCb upgrade meeting 6 SPARE February 17th 2011

Olivier Duarte / Thierry Caceres Reminder : Typical acquisition sequence LHCb upgrade meeting 7 February 17th 2011 Write Acq Register (PC) Beginning L0 sequence Time Discret Time Beginning latency delay End of latency delay 123 Recording data in RAM (512 points) FIFO full Data readout by USB 25 ns to 65,5µs Trigger Generator  PC write start sequence bit of Acquisition (Acq) Register.  Beginning of L0 sequence.  Each trigger pulse involve pulse shape.  At the end of the latency delay recording 512 points of data (Max).  At the end of the record the system write one “end of acquisition”bit in the Acq_Register.  The PC scrutinize the Acq_Register, when the “end of acquisition” is high the PC download data with the USB interface. Write Data Ctrl

Olivier Duarte / Thierry Caceres Clock tree LHCb upgrade meeting 8 February 17th 2011