Chapter 6 – MSP430 Micro-Architecture

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture2 Concepts to Learn… Computer Architecture MSP430 Micro-Architecture Instruction Cycle Review Fetch Cycle Addressing Modes Operand Fetch Cycles Execute Cycle Store Cycle Instruction Clock Cycles Digital I/O

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture3 Levels of Transformation Problems Algorithms Language (Program) Machine (ISA) Architecture Microarchitecture Circuits Devices Programmable Computer Specific Manufacturer Specific

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture4 Computer Architecture Like a building architect, whose place at the engineering/arts and goals/means interfaces is seen in this diagram, a computer architect reconciles many conflicting or competing demands. Computer Architecture

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture5 MSP430 Modular Architecture MSP430 Micro-Architecture

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture6 Memory Organization MSP430 Micro-Architecture

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture7 Micro-Architecture Simulator Memory Address Register Arithmetic Logic Unit Program Counter Address Bus Data Bus Condition Codes Memory Port 1 Output Instruction Register Source Operand Destination Operand MSP430 Micro-Architecture

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture8 Quiz… Disassemble the following MSP430 instructions: AddressData 0x8010:4031 0x8012:0600 0x8014:40B2 0x8016:5A1E 0x8018:0120 0x801a:430E 0x801c:535E 0x801e:F07E 0x8020:000F 0x8022:1230 0x8024:000E 0x8026:8391 0x8028:0000 0x802a:23FD 0x802c:413F 0x802e:3FF6

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture9 Quiz… Disassemble the following MSP430 instructions: AddressData 0x8010:4031 0x8012:0600 0x8014:40B2 0x8016:5A1E 0x8018:0120 0x801a:430E 0x801c:535E 0x801e:F07E 0x8020:000F 0x8022:1230 0x8024:000E 0x8026:8391 0x8028:0000 0x802a:23FD 0x802c:413F 0x802e:3FF6 mov.w#0x0600,r1 mov.w#0x5a1e,&0x0120 mov.w#0,r14 add.b#1,r14 and.b#0x0f,r14 push#0x000e sub.w#0,0(r1) jne0x8026 jmp0x801c

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture10 The Instruction Cycle INSTRUCTION FETCH Obtain the next instruction from memory DECODE Examine the instruction, and determine how to execute it SOURCE OPERAND FETCH Load source operand DESTINATION OPERAND FETCH Load destination operand EXECUTE Carry out the execution of the instruction STORE RESULT Store the result in the designated destination Not all instructions require all six phases Instruction Cycle

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture11 Fetching an Instruction   PC Fetch Cycle

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture12 Addressing Modes

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture13 Source Addressing Modes The MSP430 has four basic modes for the source address: Rs - Register x(Rs) - Indexed - Register - Indirect Auto-increment In combination with registers R0-R3, three additional source addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) #n – Addressing Modes

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture14 MSP430 Source Constants To improve code efficiency, the MSP430 "hardwires" six register/addressing mode combinations to commonly used source values: #0 - R3 in register mode #1 - R3 in indexed mode #4 - R2 in indirect mode #2 - R3 in indirect mode #8 - R2 in indirect auto-increment mode #-1 - R3 in indirect auto-increment mode Eliminates the need to use a memory location for the immediate value - commonly reduces code size by 30%. Addressing Modes

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture15 Destination Addressing Modes There are two basic modes for the destination address: Rd - Register x(Rd) - Indexed Register In combination with registers R0/R2, two additional destination addressing modes are available: label - PC Relative, x(PC) &label – Absolute, x(SR) Addressing Modes

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture16 Register Addressing Mode Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture17 Source: Register Mode – Rs  Rs Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture18 Destination: Register Mode – Rd  Rs Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture19 Register-Indexed Addressing Mode Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture20 Source: Indexed Mode – x(Rs)   Rs  PC  Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture21 Symbolic Addressing Mode Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture22 Source: Symbolic Mode – Address   PC   Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture23 Absolute Addressing Mode Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture24 Source: Absolute Mode – &Address   SR (0)  PC  Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture25 Register Indirect Addressing Mode Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture26 Source: Indirect Mode   Rs Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture27 Register Indirect Auto-increment Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture28 Source: Indirect Auto Mode   Rs  Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture29 Immediate Addressing Mode Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture30 Source: Immediate Mode – #n   PC Operand Fetch Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture31 Execute Phase: PUSH.W  SP  Execute Cycle

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture32 Execute Phase: Jump  Execute Cycle

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture33 Store Phase: Rd  Store Cycle

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture34 Store Phase: Other…  Store Cycle

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture35 Instruction Timing Instruction cycles = Power consumption Most instruction cycles limited by access to memory (von Neumann bottleneck) In general 1 cycle to fetch instruction +1 or immediate +2 cycles for indexed, absolute, or symbolic +1 to write destination back to memory 2 cycles for any jump No difference between byte and word Instruction Clock Cycles

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture36 Digital I/O Digital I/O grouped in 8 bit memory locations called ports Each I/O port can be: programmed independently for each bit combined for input, output, and interrupt functionality Edge-selectable input interrupt capability for all 8 bits of ports P1 and P2 Read/write access using regular MSP430 byte instructions Individually programmable pull-up/pull-down resistors The available digital I/O pins for the hardware development tools: eZ430-F2013: 10 pins - P1 (8 bits) and P2 (2 bits); eZ430-F2274: 32 pins – P1, P2, P3, and P4 Digital I/O

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture37 8-bit Digital I/O Registers Direction Register (PxDIR): Bit = 1: the individual port pin is set as an output Bit = 0: the individual port pin is set as an input Input Register (PxIN): When pins are configured as GPIO, each bit of these read-only registers reflects the input signal at the corresponding I/O pin Bit = 1: The input is high Bit = 0: The input is low Output Register (PxOUT): Each bit of these registers reflects the value written to the corresponding output pin. Bit = 1: The output is high; Bit = 0: The output is low. Note: the PxOUT is a read-write register which means previously written values can be read, modified, and written back Digital I/O

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture38 Select Digital I/O Registers Function Select Registers: (PxSEL) and (PxSEL2): PxSELPxSEL2Pin Function 00Selects general purpose I/O function 01 Selects the primary peripheral module function 10 Reserved (See device-specific data sheet) 11 Selects the secondary peripheral module function Digital I/O Port P2.0 Example: P2SEL.0ADC10AE0.0Pin Function 00General-purpose digital I/O pin 10ACLK output X1ADC10, analog input A0 / OA0, analog input I0

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture39 Interrupt Digital I/O Registers Interrupt Enable (PxIE): Read-write register to enable interrupts on individual pins on ports P1/P2 Bit = 1: The interrupt is enabled Bit = 0: The interrupt is disabled Each PxIE bit enables the interrupt request associated with the corresponding PxIFG interrupt flag Interrupt Edge Select Registers (PxIES): Selects the transition on which an interrupt occurs Bit = 1: Interrupt flag is set on a high-to-low transition Bit = 0: Interrupt flag is set on a low-to-high transition Interrupt Flag Registers (PxIFG) Set automatically when the programmed signal transition (edge) occurs PxIFG flag can be set and must be reset by software Bit = 0: No interrupt is pending Bit = 1: An interrupt is pending Digital I/O

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture40 Pull-up/down Register Pull-up/down Resistor Enable Registers (PxREN): Each bit of this register enables or disables the pull-up/pull-down resistor of the corresponding I/O pin Bit = 1: Pull-up/pull-down resistor enabled Bit = 0: Pull-up/pull-down resistor disabled. When pull-up/pull-down resistor is enabled, Output Register (PxOUT) selects: Bit = 1: The pin is pulled up Bit = 0: The pin is pulled down. Digital I/O +3.3v P2.0 P2.1 P2.3 P2.4 P2.2

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture41 Port P1 Registers Digital I/O Register Name Short FormAddress Register TypeInitial State InputP1IN020hRead only− OutputP1OUT021hRead/writeUnchanged DirectionP1DIR022hRead/writeReset with PUC Interrupt FlagP1IFG023hRead/writeReset with PUC Interrupt Edge SelectP1IES024hRead/writeUnchanged Interrupt EnableP1IE025hRead/writeReset with PUC Port SelectP1SEL026hRead/writeReset with PUC Port Select 2P1SEL2041hRead/writeReset with PUC Resistor EnableP1REN027hRead/writeReset with PUC

BYU CS/ECEn 124Chapter 6 - MSP430 Micro-Architecture42