Zynq-7000 EPP Introduction Where ARM Processors Meet HW Programmability May 2012

Demands of Today's Technology EPP FPGA ASSP Structured ASIC ASIC Which Technology Should I Choose?

Current Selections Equal Compromise ASIC ASSP 2 Chip Solution Performance +  Power - Unit Cost TCO Risk TTM Flexibility Scalability + positive, - negative,  neutral Conflicting Demands Not Served

Introducing the Zynq™-7000 EPP Breakthrough Processing Platform Higher system performance, lower total power Flexible and scalable solution Industry Standard Design Environments Well defined SW programming model Familiar SW & HW design flows Flexible Accelerators and IP World class 28nm programmable logic architecture Standard AMBA® 4 AXI interfaces Broad Ecosystem Support Tools, OS’s & IPs Middleware, codecs System integrators and training partners. Familiar Processing System + Scalable Programmable Logic

Zynq-7000 Extensible Processing Platform Next level of Programmable System Integration into a true SoC All programmable (software and hardware) processing platform ARM Cortex™-A9 MPCore™ Processing System with hardened peripherals, ADC and 28nm scalable optimized programmablel ogicc Increased System Performance 800 MHz, dual core processors with NEON and vector floating point units 7 series programmable logic (PL) with built-in DSP High bandwidth, low latency connects enable acceleration of key functions BOM Cost Advantage in an cost optimized 28nm platform Integration saves components, area and simplifies PCB Platform approach enables aggregation of volumes over several projects Lower Total Power solution Industry-leading ARM processors maximize MHz/W and low power states 28nm HPL process and Integration provides ultra-lower power data transfers Accelerated Design Productivity for TTM and TIM advantage Industry standard HW and SW development tools for fast Time-To-Market Flexible and scalable platform enables extended Time-In-Market Extensive ecosystem of tools and solutions partners

Zynq-7000 Family Highlights Complete ARM®-based Processing System Dual ARM Cortex™-A9 MPCore™, processor centric Integrated memory controllers & peripherals Fully autonomous to the programmable logic Tightly Integrated Programmable Logic Used to extend processing system High performance AXI based Interface Scalable density and performance Flexible Array of I/O Wide range of external multi-standard I/O High performance integrated serial transceivers Analog-to-Digital Converter inputs 7 Series Programmable Logic Common Peripherals Custom Peripherals Common Accelerators Custom Accelerators Common Processing System Memory Interfaces ARM® Dual Cortex-A9 MPCore™ System Software & Hardware Programmable

Zynq-7000 Device Portfolio Summary Scalable Platform offers easy migration between devices Zynq-7000 EPP Devices Z-7010 Z-7020 Z-7030 Z-7045 Processing System Processor Core Dual ARM® Cortex™-A9 MPCore™ Processor Extensions NEON™ & Single / Double Precision Floating Point Max Frequency 800MHz Memory L1 Cache 32KB I / D, L2 Cache 512KB, on-chip Memory 256KB External Memory Support DDR3, DDR2, LPDDR2, 2x QSPI, NAND, NOR Peripherals 2x USB 2.0 (OTG), 2x Tri-mode Gigabit Ethernet, 2x SD/SDIO, 2x UART, 2x CAN 2.0B, 2x I2C, 2x SPI, 4x 32b GPIO   Programmable Logic Approximate ASIC Gates ~430K (30k LC) ~1.3M (85k LC) ~1.9M (125k LC) ~5.2M (350k LC) Extensible Block RAM 240KB 560KB 1,060KB 2,180KB Peak DSP Performance (Symmetric FIR) 58 GMACS 158 GMACS 480 GMACS 1080 GMACS PCI Express® (Root Complex or Endpoint) - Gen2 x4 Gen2 x8 Agile Mixed Signal (XADC) 2x 12bit 1Msps A/D Converter I/O Processor System IO 130 Multi Standards 3.3V IO 100 200 212 Multi Standards High Performance 1.8V IO 150 Multi Gigabit Transceivers 4 16

Delivering Highest Customer Value Build better processing systems with fewer chips … faster Build better systems faster Increased System Performance BOM Cost Reduction Total Power Reduction Accelerated Design Productivity Programmable Systems Integration

Programmable Systems Integration Increased System Performance BOM Cost Reduction Total Power Reduction Accelerated Design Productivity ALL Programmable Platform Integrating Multiple Components Hardware and Software programmable Board component reduction Security & reliability Manufacturing benefits Defines Extensibility Create custom, flexible ASSP Co-processing offload by accelerating software functions ARM Programmability + FPGA Flexibility in a Single Chip

Increased System Performance Programmable Systems Integration Increased System Performance BOM Cost Reduction Total Power Reduction Accelerated Design Productivity Hardware Performance Dual Core ARM Cortex A9’s with NEON and vector floating point High performance programmable logic Tightly coupled processor and programmable logic High throughput / low latency Massive parallel DSP processing High performance I/Os and transceivers (12.5Gbps) Accelerating Processor Performance Increasing software performance through co-processing accelerators Low latency interfacing for efficient co-processor implementation Elements Performance (up to) Processors (each) 800 MHz Processors (aggregate) 4000 DMIPs DSP (each) 600MHz DSP (aggregate) 1080 GMACs Transceivers (each) 12.5Gbps Transceivers (aggregate) 200Gbps SW Acceleration using PL >10x Optimized Balance of Performance and Power

Platform approach enables aggregation of volumes for lower price BOM Cost Reduction Programmable Systems Integration Increased System Performance BOM Cost Reduction Total Power Reduction Accelerated Design Productivity Reduced Devices per Board Processors, PLDs, DSPs A/D converters Power supplies, fans, etc… Reduced PCB Complexity Fewer traces/interconnect/layers Fewer power supplies Smaller overall PCB In System Reconfiguration Combines Multiple Device Functions HW can be configured and reconfigured only with the needed function at a given time PS Aggregates Numerous IP Royalties for Net Cost Benefit ASIC or full FPGA solutions would require purchase of these IPs from 3rd parties. Up to 40% BOM Cost Reduction vs. Multi-Chip Solutions Platform approach enables aggregation of volumes for lower price

Significant Power Reduction at the System Level Total Power Reduction Programmable Systems Integration Increased System Performance BOM Cost Reduction Total Power Reduction Accelerated Design Productivity Flexible/Tunable Power Envelope Adjustable processor speed Adjustable ARM AMBA®- AXI & memory speeds ARM low power states Programmable logic can be turned off Programmable logic clock gating Partial reconfiguration to reduce Programmable logic requirement Integration Power Reduction Reduced interconnections between devices Fewer system devices Lower programmable logic power (28nm HPL process) Up to 50% Lower Power Vs. Multi-Chip Solutions Significant Power Reduction at the System Level

Accelerated Design Productivity Programmable Systems Integration Increased System Performance BOM Cost Reduction Total Power Reduction Accelerated Design Productivity Reduced Time To Market Fixed processor system across family Scalable optimized architecture for IP re-use / AXI interfaces for plug & play IP Accelerate developments with targeted design platforms Increased Time In Market Software and hardware re-programmability Field upgradable Address ASSPs short shelf life Industry Leading Tools Development tools Xilinx platform studio (XPS), software developers Kit (SDK), IDS for programmable logic development and PS configuration Support for 3rd party SW tools – (any Cortex-A9 tool should just work) Development platforms Emulation platform, virtual platform, development boards Extensive Ecosystem Strong and rapidly growing global partner and other 3rd party support Industry leading OS’s, tools, IP, system integration/design houses Dev. Design #1 Platform #1 Design #3 Design #2 ASIC / ASSP / 2 Chip EPP Extended Product life

Zynq-7000 EPP Value Proposition ASIC ASSP 2 Chip Solution Zynq-7000 Performance +  Power - Unit Cost TCO Risk TTM Flexibility Scalability + positive, - negative,  neutral Conflicting Demands Now Served by the Zynq-7000 Family

Designing with Zynq-7000 EPP

Zynq-7000 EPP Platform Offering Applications Libraries & APIs Custom OS BSP’s OS Kernel High Level and Low Level Drivers Reference Design & Board Virtual Platform Processing System Programmable Logic Silicon SW Development Tools SW & HW IP HW Development Tools More Than Just Silicon – A Comprehensive Platform Offering.

Developments Environments End-to-End Tools Xilinx SDK ARM Ecosystem Open Source Huge SW Base Xilinx ARM libraries RTOS and OS vendors Middleware Industry-leading Tools High Level Synthesis VHDL/Verilog: From Design Entry to Implementation Simulation Timing, power, signal analysis Many Sources of HW IP Xilinx Library 3rd Party Custom High Level Functions Standardized around AXI

Zynq-7000 EPP SW Development Environment ARM-standard Development with Xilinx Flexibility Standard ARM Instruction Set and APIs AXI support Easy software migration from other ARM-based systems Leverage ARM Worldwide Ecosystem Tools OS, Middleware, Libraries Professional Services 3rd Party Open Source Community Board Support Package, Drivers and Custom IP Cores Provided for a range of development boards, peripherals and system functions Applications OS Kernel High Level and Low Level Drivers Processing System Programmable Logic OS BSP’s Silicon Custom Libraries & APIs

Zynq-7000 EPP HW Design Environment Customize your Design Create a unique microprocessor configuration Realize DSP, graphics, communications functions Design custom accelerators and functions Deploy high level functions directly to silicon Xilinx-Optimized EDA Design tools HDL & HLS simulation HDL synthesis Design analysis Integrate Plug & Play IP Portfolio AMBA® AXI enabled Large selection of Xilinx and 3rd Party IP Applications OS Kernel High Level and Low Level Drivers Processing System Programmable Logic OS BSP’s Silicon Custom Libraries & APIs

Zynq-7000 EPP Development Platforms Powerful Xilinx Development Platforms ZC702 Base Evaluation Kit Zynq-7000 EPP Video Kit Many Application Specific Development Kits Expandable with Industry Standards FMC (FPGA Mezzanine Connector) Daughter Cards QEMU Virtual Platform Various Partner development Platforms Community based AVNET ZedBoard Many local and worldwide COTS providers Cadence Virtual Platform

Extensive Partnership Ecosystem And MORE …

Zynq-7000 EPP – Platform Availability HW Design Tools ISE Design Suite 14.1 Virtual Platform 3 options: QEMU, Software Developer System Creator Tools Ecosystem 7000 OS Ecosystem Linux, Android, WinCE, VxWorks, ENEA OSE, FreeRTOS, … Other partners IP FPGA Blocks Software elements Design Services (Boards and Applications) Trainings Silicon Devices Dev. Boards

Zynq-7000 Extensible Processing Platform Summary New Scalable Family of Devices Zynq-7000 EPP device portfolio Four devices for a broad range of applications Industry Standard Design Environments Well defined SW programming model Familiar HW design flow Flexible accelerators and IP Standard AMBA® AXI interfaces Broad and Expanding Ecosystem Tools, OS’s, IP Middleware, codecs … Availability Z-7020 Sampling Now Production 2H CY2012 7000 7010 30 7020 85 7030 125 7045 350

Zynq-7000 EPP Driver Assistance Application

Zynq-7000 EPP Broadcast Camera Application

Zynq-7000 EPP Broadcast Camera Application

Device Table

Zynq-7000 Device Table Processing System

Zynq-7000 Device Table Programmable Logic and Packages