Using VHDL VHDL used for Simulation Synthesis.

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Presentation transcript:

Using VHDL VHDL used for Simulation Synthesis

Example: Electronic Lock

Behaviour Model of Electronic Lock

Gate Implementation of MUX

VHDL Description

Synthesized Circuit uses Internal Component from vendor’s Library

AND Gate as a Process signal A, B, C : bit; process ( A, B) is begin C < = A and B; end process; -- Shortcut: c <= A and B;

Processes run concurrently architecture structure of ent1 is architecture flow of ent1 is signal Int1, Int2 : std_logic; signal Int1, Int2 : std_logic; begin begin Int1 <= A or C; GATE1 : process (A,C) is Int2 < = B or D; begin Out <= Int1 and Int2; Int1 <= A or C; end flow; end process; GATE2 : process (B,D) is Int2 <= B or D; GATE3 : process (Int1, Int2) is Out <=Int1 and Int2; end structure;

Fitting the Circuit onto PLD A Fitting Tool uses the netlist generated by the synthethiser to place the circuit onto the chip. The post-fit (known as timing) simulation reflects the combined “reality” of the netlist and the way all the components and their interconnections were placed on silicon. It is the closest one can get to a “real” circuit!!!