DIGITAL DESIGN WITH VHDL Exercise 1 1Muhammad Amir Yousaf.

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Presentation transcript:

DIGITAL DESIGN WITH VHDL Exercise 1 1Muhammad Amir Yousaf

What is VHDL? What it is used for? 2Muhammad Amir Yousaf

VHDL vs Programming languages? 3Muhammad Amir Yousaf

VHDL VERY HIGH SPEED INTEGRATED CIRCUIT HARDWARE DESCRIPTION LANGUAGE: Origininally designed to describe and specify hardware. Specifications were made executable with simulators. Synthesizer were developed to synthesize. 4Muhammad Amir Yousaf

VHDL - MODULARITY Component in VHDL is refferd as ’entity’ and has a clear interface. Inputs Outputs Type and size. Internal of component is called architecture declaration. Complexity is hidden inside. Made of components and wires. How the external world would see it. 5Muhammad Amir Yousaf

DESCRIPTION OF A DIGITAL COMPONENT. A component is to be designed with following description: A full adder that adds two 1 bit inputs and a carry- in bit. The result is shown at a 1 bit SUM and a carry-out bit. Describe this component in (a standard descriptive language) VHDL Full Adder A B CIN SUM COUT 6Muhammad Amir Yousaf

DESCRIPTION OF A FULLADDER WITH VHDL Full Adder A B CIN SUM COUT 7Muhammad Amir Yousaf

DESCRIPTION OF A DIGITAL COMPONENT. A component is to be designed with following description: A full adder that adds two 1 bit inputs and a carry- in bit. The result is shown at a 1 bit SUM and a carry-out bit. Describe this component in (a standard descriptive language) VHDL Full Adder A B CIN SUM COUT Let add a ‘RESET’ pin in the component. RST 8Muhammad Amir Yousaf

DESCRIPTION OF A DIGITAL COMPONENT. VHDL code: If RST = ’1’ then SUM <= ‘0’; COUT <= ‘0’; else End if;  If is sequential, so must be contained in process.  Sequential or procedural statements execute in the order as they appear in code. label: process ( ) 9Muhammad Amir Yousaf

DESCRIPTION OF A FULLADDER Full Adder A B CIN SUM COUT RST 10Muhammad Amir Yousaf

EXERCISES EX 1: Describe a system in VHDL with an input x and output y of type integer. The system gives x+10 at output whenever a change is detected on input. EX 3: A MUX is described in VHDL as. MUX Make a 4-to-1 MUX using the structure of 2-to-1 MUXs. EX 2: ´Describe a 4-bit comparator in VHDL using relational operators i.e > < =. comp 4 4 x y gt eq lt 11Muhammad Amir Yousaf

A MODEL OF A DIGITAL SYSTEM IS DESCRIBED IS IT TIME TO TRANSLATE IT IN HARDWARE? IS IT POOSIBLE TO SEE AND ANALYZE THE SYSTEM PERFORMANCE? CAN WE SIMULATE THE RESULTS? 12Muhammad Amir Yousaf

SIMULATING DESCRIPTION OF DIGITAL DESIGN  A digital component is modeled in VHDL but not proven yet.  Model a ’TESTBENCH’ in VHDL to prove the performance of designed part.  ’TESTBENCH’ applies stimulus to the design and simulates the response of system. In stimulus we assign inputs to the system. 13Muhammad Amir Yousaf

TESTBENCH Stimulus TESTBENCH Full Adder A B CIN SUM COUT RST Full Adder A B CIN SUM COUT RST 14Muhammad Amir Yousaf

TESTBENCH BY XILINX 15Muhammad Amir Yousaf

TESTBENCH BY XILINX 16Muhammad Amir Yousaf

PRACTICAL LET WE MODEL THIS IN VHDL WITH XILINX START XILINX 17Muhammad Amir Yousaf

SYNTHESIZE LET TRANSLATE OUR MODEL INTO HARDWARE DIGILENT NEXYS2 User IOs  8 slide switches.  8 LEDs  4 push buttons  4 seven segment displays Full Adder A B CIN SUM COUT RST 18Muhammad Amir Yousaf

SYNTHESIZE FPGA User IOs  8 slide switches.  8 LEDs  4 push buttons  4 seven segment displays.ucf file gives connection mapfile Top VHDL file Gives top interface of the system. Use Adept from Digilent to load the bit file in FPGA. 19Muhammad Amir Yousaf

Home Exercise: VGA: Read about VGA controller to know that how it works. VGA reference document and VHDL code is given at: 20Muhammad Amir Yousaf