Programmable Logic Training Course Custom Options

Main Menu Options User Constraints Option – Use to user defined P&R and timing control condition for current implementation – Specify constraint file (optional) Implementation, Simulation and Configuration Options – Implementation has four sub- menus: Optimize and Map, Place and Route, Timing, and Interface The key choices for each sub-menu will be discussed Design -> Implement -> Options

Start and Stop the GUI Select Flow Engine -> Setup -> Advanced to select the starting state Select Flow Engine -> Setup -> Stop After to set stopping point

Optimization and Map Options  The GUI includes these options: Trim Unconnected Logic –Trims logic from the design Replicate Logic to Allow –Reduces levels of logic to minimize delay –Increases utilization Generate 5input Functions –Reduces block levels but increases area CLB Packing Strategy –Informs Map of how to pack COMPS with logic Map optimizes the design before it is partitioned into LUTs, Flip-Flops, etc. Flow Engine -> Setup -> Options -> Edit Implementation Template -> Optimize and Map Tap

Place and Route Options Placement Options – Trades off placement effort versus CPU time Router Options – The Router will run until no improvement is made to meet timing constraints. – Specify a number to avoid very long run times for difficult designs – Start with three passes Design -> Implement-> Options -> Edit Implementation Template -> Place and Route Tap

Advance Place and Route Options (1) Select Design Version on the Design Manager Select Design -> FPGA Multi Pass Place and Route PAR Multi-Pass Place and Route executes multiple Place and Route jobs Design -> FPGA Multi Pass Place and Route

Advance Place and Route Options (2) PAR Multi-Pass Place and Route options – Initial Placement Seed - determines algorithms used for placement * Automatically incremented for each pass * There is no method to predict which strategy will produce the best results for a given design –Place and Route Passes to Execute - specifies the number of passes –Final PAR report reports relative design scores * Scores are judged on critical path results and routing resources used –Save N Best - specifies the number of routed designs to save * PAR saves the best implementations, which have the lowest scores *Typically three

Advance Place and Route Options (3) How many passes should be run? Here are a few estimates based on family: –3K, 5K, and smaller 4KE/XL devices passes –Mid-range 4000E/4000XL devices passes –XC4028EX/XL and XC4036EX/XL passes –XL devices > XC <3 passes Guidelines are based on length of time to run passes –Guidelines above assume a run time of ~10 hours on a SPARC 10 workstation Other factors which effect runtime: –Loose timespecs decrease runtime of each pass –As percent of device used by design increases, run time increases –Larger devices will take longer to place and route

Timing Report Options Enable the creation of the Timing Report –Logic Level Timing Report is created after MAP *Has minimal net delays *Used to analyze constraints for realistic constraints –Post Layout Timing Report is created after PAR *Verify that the design meets constraints Design -> Implement -> Options

Interface Option Described in Simulation and Design Manager sections Design -> Implement -> Options -> Edit Simulation Template

Programmable Logic Training Course Constraining the Design

Constraint Entry Overview All constraints are entered in a User Constraint File (UCF) Some synthesis tools allow entry of constraints –Constraint files may be generated by the synthesis tools, or constraints may be written in output netlist –Check the vendor interface UCF file syntax is given in this chapter One UCF file is defined per design Timing constraints may also be defined in schematic –Advantage: Easy entry for hierarchical blocks *UCF files must have hierarchical net and component names –Disadvantage: Not all constraints are supported –See Libraries guide for schematic syntax and availability

UCF Syntax Use uppercase letters for keywords –Keywords include names used in constraints, such as: AFTEROFFSETPERIOD BEFORE NETINOUTLOC Use quotes around names with non- alphanumeric characters Two types of wildcards may be used: –“?” is a wildcard for a single character –“*” is a wildcard for any number of characters

Pin Location / Implementation Constraints Pads can be assigned to a package pin –The following example assigns a bus signal to pin 32 INST “QOUT ” LOC = P32; Physical Implementation may be controlled in the UCF file, such as: FAST: Set fast I/O slew rate Example: INST “$1I87/OBUF” FAST; PART: Define part type to be used Example: CONFIG PART=4005E-PQ160C-5;

Consider the following path: Assume system requirements dictate a delay of 27 ns for all input to output pins The TIMESPEC constraint communicates this requirement to software: TIMESPEC TS01 = FROM PADS TO PADS 27 NS; PAD-to-PAD TIMESPECS constrain the delay of input and output pads, and all net and block delays in the path Simple Combinatorial Path B OUT2 27 NS A 2 levels of logic

Sync I/O Constraints (1) Timing requirements for the design are described by defining system delays System delay include these questions: –What is the clock period? –When do inputs arrive at IC2? –When must outputs be stable to meet setup at IC3? IC1 IC2 : FPGA Under Development IC3 CLOCK

Sync I/O Constraints (2) Consider constraints on the I/O Example: –Data is clocked by signal CLK on all ICs –Frank is creating IC2 *All inputs and outputs of IC2 are synchronized to CLK *How are inputs and outputs constrained? IC2: Device under Development IC 1 IC 3 D CK Q C2 C3 C1 C4 D CK Q CLK D CK Q

Sync Constraint Example OFFSET defines the delay of a signal external to the chip, relative to a clock. Internal clock delays are determined by Software FF1FF2 40ns Determined by Software Tarrival 14ns Tstable 12ns Determined by Software ADD0_IN CLK 28 OUT1 NET “CLK” PERIOD = 40; NET “ADD0_IN” OFFSET = IN 14 AFTER CLK; NET “ADD0_OUT” OFFSET = OUT 12 BEFORE CLK;

Input Arrival Calculation Inputs are constrained by their input arrival. Example: When does data arrive at pin D1? –After the clock trigger, data delay is TCKO + Tnet + Tpad + TC1 –Delay C1 net delays, or other combinatorial elements on the board –Delay TCD is the delay through the FPGA clock distribution network Tarrival = Tcko + Tnet + Tpad + TC1 - TCD 050 Tarrival CLK IC 1 D Q C1 Tcko Tnet Tpad Tc1 IC2: Device under Development C2 D CK Q D1 Tcd Tpad

Output Stability Calculation When does output data need to be stable? –Data must be stable in order to meet the setup requirement for IC3 –How long must the data be stable before data is latched in IC3? * Tstable = Tc3 + Tpad + Tnet + Tc4 + Tsetup + TCD *TCD is the delay through the clock distribution network Tstable = Tc3 + Tpad + Tnet + Tc4 + Tsetup + TCD 0 50 Tstable IC2: Device under Development IC 3 C2 C3 C4 D CK Q D Q CLK Tsetup Tnet Tpad Tc4 Tc3 O1

Period and Offset Constraints Two commands are used to describe synchronous delays –Period defines the clock –Offset constraints define input arrival time and output stability time relative to the clock Xilinx software determines internal FPGA delays from Period and Offset constraints Syntax: NET clock_name PERIOD = some_delay time_unit; NET input_name OFFSET = IN Tarrival time AFTER clock_name; NET output_name OFFSET = OUT Tstable BEFORE clock_name; (Input_name and output_name are the names of nets connecting to the IO Pad)

Clock Constraint Example Use the Period Command to define the clock Given that the clock frequency is 20 MHz for the example: NET “CLK” PERIOD = 50 ns; Example waveform for CLK

Constraint Recommendations Do not use the same TIMESPEC name for more than one path Keep constraints in one source –Either UCF file or in schematics, but not both Avoid OVER-constraining the design –Design Performance suffers *Critical timing paths get the best placement and fastest routing options *As the number of critical paths increases, routability decreases –Run times increase –The appendix shows ways to avoid over-constraining

Questions What is the function of this statement INST QOUT = P32; ? Given the following: Clock Frequency = 20 MHz Tarrival = 31 ns = delay from CLK to Input pin D1 of IC2 Tstable = 27 ns = Delay (include setup) from O1 to D pin of FF3 (IC3) NET _____ PERIOD = _____ NS; NET _____ OFFSET = IN _____ AFTER CLK; NET _____ OFFSET = OUT _____ BEFORE CLK; Fill in the constraints below : IC2: Device under Development CLK IC 1 IC 3 D CK Q C2 C3 C1 C4 D CK Q D Q D1 O1

Path & Block Specific Constraints In this appendix, consideration is given to constraints which only apply to a specific block or path. Why use path or block specific constraints? –To decrease speed requirements wherever possible –To Increase routability and overall speed of the design –To decrease software run-time General Methodology –Use Period and Offset to constrain the design globally –Use specific constraints to modify timing for certain blocks or paths

“FROM-TO” Constraint Exam(1) Consider the example shown below with TIMESPEC: TIMESPEC TS01 = FROM PADS TO PADS 21; TS01 is applied to both Y - OUT1 and Z - OUT2. 21 ns FF1FF2 OUT1 CLK X Y Z OUT2 1 Level of Logic 2 Levels of Logic 21 ns

“ FROM-TO” Constraints (1) The two paths could be constrained with two commands: TIMESPEC TS01 = FROM PADS(Y) TO PADS(OUT1)21; TIMESPEC TS02 = FROM PADS(Z) TO PADS(OUT2)28; “FROM:TO” Constraints can start and stop at Flip-Flops, LATCHES, PADS, or RAMS Examples: –Constrain all inputs to all Flip-Flops in block NEWFIE: TIMESPEC TS03 = FROM PADS TO FFS(NEWFIE)18ns; –Constrain all Flip-Flop to Flip-Flop paths in the design: TIMESPEC TS04 = FROM FFS TO FFS 15ns; –Constrain all Flip-Flop to output paths in the design: TIMESPEC TS05 = FROM FFS TO PADS 25ns;

“FROM-TO” Constraints (2) GLOBAL “FROM-TO” constraints may apply to all paths of a certain type using keywords or pre- defined groups –Example: TIMESPEC TS03 = FROM PADS TO FFS18 ns; Legal keywords (pre-defined groups) are PADS, FFS, LATCHES, and RAMS Recommendation for best run-time: –Use Period and OFFSET for global constraints –Use “FROM-TO” type for blocks or paths within the design Exception: –OFFSET may only be defined in a UCF file –“FROM-TO” constraints may be defined in schematics

Creating Groups with TNM The TNM constraint creates a group of individual components Example: create divide Flip-Flops into two groups based on instance name INST SLOWFF* TNM = SLO; INST FASTFF* TNM = FST; TIMESPECS are assigned to the new groups : TIMESPEC TS14 = FROM FFS TO SLO 40 NS; TIMESPEC TS15 = FROM FFS TO FST 20 NS; Greater flexibility in routing is achieved by creating a different timing requirement for these two groups of Flip-Flops SLOWFF2 SLOWFF1 FASTFF1 FASTFF2 REG1 REG2 COMB3

Pre-Scaled Counter Example Highest speed is required in the pre-scaled block –Constrain the two counter blocks separately to avoid over-constraining COUNT12 Define two groups for use in TIMESPEC. –Example UCF file: INST FFS(PRE2) TNM = PRE; INST COUNT12 TNM = UPPER; TIMESPEC TS_PRE = FROM PRE TO PRE 60 MHZ; TIMESPEC TS_TC2CE = FROM PRE TO UPPER 60 MHZ; TIMESPEC TS_UPPER = FROM UPPER TO UPPER 15 MHZ; Q5 Q6Q3 Q4 Q9 Q10 Q7 Q8 Q13 Q11 Q12 Q2 COUNT12 Q0 Q1 PRE2 TCCE

Creating Groups with TIMEGRP Another way to constrain this design is by creating smaller groups of endpoints: The TIMEGRP constraint is used to create new groups from other groups. FFS, LATCHES, RAMS, and PADS are predefined groups Example: ALL_FFS group contains all Flip-Flops whose instance name begins with SLOWFF or FASTFF: INST SLOWFF* TNM = SLO; INST FASTFF* TNM = FST; TIMEGRP ALL_FFS = FFS (FST* : SLO*) ;

Creating Sub-groups with EXCEPT “Except” is another way to filter a group of endpoints. For example: INST FASTFF* TNM = FST; TIMEGRP SLO = FFS EXCEPT FST; Then, group SLO can be used in other timespecs: TIMESPEC TS14 = FROM FFS TO SLO 40 NS; TIMESPEC TS15 = FROM FFS TO FST 20 NS; Greater flexibility in routing is achieved by creating these two groups

Select One Path From Many Paths Use to constrain one path among several parallel paths First identify the path to be constrained with TPTHRU, then use THRU in Timespec constraint Example: constrain the path through component ABC fiforam my_reg01 my_reg00 my_reg02 my_reg03 TPTHRU=ABC NET RED TPTHRU = ABC; TIMESPEC TS_FIFOS = FROM RAMS(FIFORAM) THRU ABC TO FFS(MY_REG*) 25; RED

Create of Combination Endpoint TPSYNC allows definition of end points that are not FFS, RAMS, PADS or LATCHES. –Commonly used with Three-State Buffers –Use the TPSYNC constraint to specify internal combinatorial endpoints First create the TPSYNC endpoint, then use it in a TIMESPEC like any other endpoint Example: TIMESPEC TS_1A applies to the path from FF5 to the inputs of the combinatorial logic. FF5 D CLK COMB_B BLUE COMB_A NET “BLUE” TPSYNC = BLUE_S; TIMESPEC TS_1A = FROM FFS TO BLUE_S 15 NS ;

Forward Tracing Forward tracing occurs when a constraint is assigned to a net Constraint is applied to all global endpoints driven by the net Example: constrain nets driven by DATA0 to Flip-Flops in block CNT25: NET “DATA0” TNM = MYBUS; TIMESPEC TS_REGCNT = FROM MYBUS TO FFS(CNT25) 30 NS;... CHEW BONE DATA0 BARK CNT25 TS_REGNCT

Ignore Paths with TIG and NET The TIG attribute ignores a TIMESPEC for a specific path or net Example for multiple constraints: “NET” is used to assign TIG to a net Assume that net DOG_SLOW was constrained by 2 constraints, TS01 and TS02. The following specification ignores TS01. TS02 only is applied to DOG_SLOW. NET “DOG_SLOW” TIG = TS01; Example to ignore a slow path between registers: INST REGA* TNM = REGA; INST REGB* TNM = REGB; TIMESPEC TS_TIG01 = FROM FFS (REGA) TO FFS(REGB) TIG; IMPORTANT NOTE: TIG improves software run-time and routability of the design

Ignore Path go to through a TBUF If a design has a bi-directional bus with sets of registers in different blocks. There can be a false path from control registers through the TBUF to the status registers. NET “DATA_BUS*” TPTHRU = DATABUS; TIMESPEC TS_TIGDATA=FROM FFS THRU DATABUS TO FFS TIG; DATA_BUS(7:0) Control Register Status Registers Control_EnableStatus_Enable

Limiting Skew Signal SKEW may also be constrained using the MAXSKEW constraint –NET “$1I3245/$SIG_6” MAXSKEW = 3; –I.e. specifies a 3 ns difference between the arrival times at all destinations of net $1I3245/$SIG_6. May use to control skew of logic driven by clocks Cannot constrain skew of global nets (skew is fixed)

Constraint Priority All constraints are not created equal –Highest Priority- Timing ignores ( TIG ) - FROM:THRU:TO specs / FROM:TO specs –Lowest Priority- PERIOD specs “FROM:TO” constraints are further prioritized: –Highest: FROM PATH-SPECIFIC TO PATH_SPECIFIC FROM PATH-SPECIFIC TO GLOBAL –Lowest: FROM GLOBALTO GLOBAL Over-constraining the design can decrease routability and increase run time –Use for slower & lower priority global constraints Period constraints Use faster timespecs for: –Higher priority path-specific constraints /THRU constraints Priorities can be explicitly within a constraint CLASS –Low numbers specify high priority – TIMESPEC TS01 = FROM A to B 40 PRIORITY 3;

Programmable Logic Training Course Configuration

Bitstream Generator Bitstream Generator will run if Produce Configuration Data is selected. Although the Produce Configuration Data switch is asserted by default, turning the switch off will save implementation time.

Configuration Method

Tips for Configuration Debug Check VCC and Rise time Check Configuration pins and contention Check for Clean connections between FPGA and source Watch timing requirements in peripheral and slave modes Examine DOUT and CCLK outputs even if not used Try XChecker cable or different FPGA Debug daisy chain one at a time, in sequence order –Put latest family first

Master Serial Mode FPGA automatically loads itself from external serial PROM –Requires one small chip, few connections –Xilinx offers serial PROMs from 18K to 256K Internal CCLK clocks address counter in the serial memory Serial PROM Serial PROM FPGA CCLK Enable Data Reset

Master Parallel Mode FPGA automatically loads itself from external byte-wide PROM –Can use part of existing PROM Internal CCLK clocks address counter in FPGA –Up from 0 or Down from all 1’s, specified by mode –16-22 bit address for large FPGA, or large daisy chain Data is still serialized internally (configures at same rate) Parallel PROM Parallel PROM FPGA Address Enable Data

Peripheral Mode FPGA loads under microprocessor control as a peripheral May not require extra connections if FPGA is already connected to a processor –Byte of data supplied by external controller –FPGA reads data when Chip Selects and Write asserted –FPGA Ready/!Busy signal indicates ready for next byte FPGA Data Write Strobe Chip Selects Ready/Busy

Synchronous Peripheral Mode XC4000/XC5000 only User generates configuration clock, CCLK Accepts byte-wide data FPGA Data CCLK Ready/Busy

Slave Mode Simple two-wire interface FPGA reads one bit of data on each clock supplied externally Can be controlled by microprocessor or DMA controller Used by XChecker download cable FPGA Micro- processor Micro- processor Data CCLK

Daisy Chain Can program multiple devices with independent configurations from one PROM Control from lead FPGA in daisy chain –Lead FPGA can be in any configuration mode –Following FPGAs must be in slave mode Automatically created by PROM Formatter Slave FPGA Slave FPGA Lead FPGA Lead FPGA PROM Slave FPGA Slave FPGA Address Control Data Clock Data BITSTREAM1 BITSTREAM2 BITSTREAM3 BITSTREAM1BITSTREAM2BITSTREAM3 DOUT DIN