A Low-Power 4-b 2.5 Gsample/s Pipelined Flash Analog-to-Digital Converter Using Differential Comparator and DCVSPG Encoder Shailesh Radhakrishnan, Mingzhen Wang and Chien-In Henry Chen. Department of Electrical Engineering Wright State University Dayton, USA, May,2005. 班級 ：積體碩一 姓名 ：黃順和 學號 ：95662009

outline 1. Introduction 2. Pipelined Flash ADC 3. Track-and-Hold Circuit 4. Differential Comparator 5. DCVSPG Encoder 6. Experimental Results 7. Conclusions 8. References

Introduction Dual-array T/H achieves higher data throughput. The proposed ADC uses current mode, dual-array T/H. Differential comparator has less susceptible to noise than TIQ comparator. Power consumption of the differential comparator is much less as compared to the TIQ comparator. This paper presents a DCVSPG (differential cascode voltage switch with pass-gate) encoder which directly converts the thermometer code to binary code in one step.

Pipelined Flash ADC

Track-and-Hold Circuit

Differential Comparator

DCVSPG Encoder

Experimental Results The 4-bit flash ADC is designed and simulated in 130 nanometer CMOS. Both INL and DNL as shown in the table are less than 0.3 LSB. The average power consumption is 23.78 mW. The simulation of the ADC with 250 MHz input signal. The power consumption of the DCVSPG encoder is 88 % less than the conventional ROM encoder.

ENCODER PERFORMANCE SUMMARY

PERFORMANCE OF 4-BIT ADC

Conclusions The pipelined architecture achieves high data throughput and high speed by incorporating pipelined clocked track-and-hold and clocked DCVSPG encoder. The pipelined CMOS ADC offers a data conversion rate of 2.5 GSPS while maintaining low power consumption. The DCVSPG encoder overcomes the speed limitation of the ROM encoder which has been a bottleneck of high-speed ADCs.

References [1] F. Lai and W. Hwang, “Design and implementaion of differential cascode voltage switch with pass-gate (DCVSPG) logic for highperformance digital systems,” IEEE Journal of Solid-State Circuits, vol. 32, April 1997. [2] J. Yoo, K. Choi, and J. Ghaznavi, “Quantum voltage comparator for 0.07 μm flash A/D converters,” Proceedings of the IEEE Computer Society Annual Symposium on VLSI, pp. 20-21, Feb. 2003. [3] X. Jiang, Z. Wang and M.F. Chang, “A 2GS/s 6-b ADC in 0.18 μm CMOS,” IEEE International Solid-State Circuits Conference, vol. 1, pp. 9-13, Feb. 2003