EE415 VLSI Design THE INVERTER DYNAMICS [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

EE415 VLSI Design Inverter Dynamics  Dynamic Behavior  Delay Definitions  Voltage Transfer Characteristic  Switching Threshold  Propagation Delay  Transient Response  Inverter Sizing  Power Dissipation  Short Circuit Currents  Technology Scaling

EE415 VLSI Design Dynamic Behavior Propagation Delay, T p Defines how quickly output is affected by input Measured between 50% transition from input to output t pLH defines delay for output going from low to high t pHL defines delay for output going from high to low Overall delay, t p, defined as the average of t pLH and t pHL

EE415 VLSI Design Dynamic Behavior Rise and fall time, T r and T f Defines slope of the signal Defined between the 10% and 90% of the signal swing Propagation delay and rise and fall times affected by the fan-out due to larger capacitance loads

EE415 VLSI Design Delay Definitions

EE415 VLSI Design The Ring Oscillator A standard method is needed to measure the gate delay It is based on the ring oscillator 2Nt p >> t f + t r for proper operation

EE415 VLSI Design Ring Oscillator

EE415 VLSI Design Voltage Transfer Characteristic

EE415 VLSI Design CMOS Inverter Load Characteristics G S D G S

EE415 VLSI Design PMOS Load Lines V DSp I Dp V GSp =-5 V GSp =-2 V DSp I Dn V in =0 V in =3 V out I Dn V in =0 V in =3 V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp V out I Dn V in = V DD +V GSp I Dn = - I Dp V out = V DD +V DSp G S D G S

EE415 VLSI Design CMOS Inverter Load Lines 0.25um, W/L n = 1.5, W/L p = 4.5, V DD = 2.5V, V Tn = 0.4V, V Tp = -0.4V I Dn (A) V out (V) X V in = 1.0V V in = 1.5V V in = 2.0V V in = 2.5VV in = 0V V in = 0.5V V in = 1.0V V in = 1.5V V in = 0.5V V in = 2.0V V in = 2.5V V in = 2V V in = 1.5V V in = 1V V in = 0.5V V in = 0V PMOSNMOS

EE415 VLSI Design CMOS Inverter VTC V in (V) V out (V) NMOS off PMOS res NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off

EE415 VLSI Design CutoffLinearSaturation pMOS V in -V DD = V GS > V T V in -V DD =V GS < V T V in -V out =V GD < V T V in -V DD =V GS > V T V in -V out =V GD >V T nMOS V in = V GS < V T V in =V GS > V T V in -V out =V GD > V T V in =V GS > V T V in -V out =V GD < V T G S D G S Regions of operations For nMOS and pMOS In CMOS inverter

EE415 VLSI Design CMOS Inverter Load Characteristics For valid dc operating points: current through NMOS = current through PMOS => dc operating points are the intersection of load lines All operating points located at high or low output levels => VTC has narrow transition zone high gain of transistors during switching transistors in saturation high transconductance (g m ) high output resistance (voltage controlled current source)

EE415 VLSI Design Switching Threshold l V M where V in = V out (both PMOS and NMOS in saturation since V DS = V GS ) V M  rV DD /(1 + r) where r = k p V DSATp /k n V DSATn l Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors l Want V M = V DD /2 (to have comparable high and low noise margins), so want r  1 (W/L) p k n ’V DSATn (V M -V Tn -V DSATn /2) (W/L) n k p ’V DSATp (V DD -V M +V Tp +V DSATp /2) =

EE415 VLSI Design Switch Threshold Example In 0.25  m CMOS process, using parameters from table, V DD = 2.5V, and minimum size NMOS ((W/L) n of 1.5) V T0 (V)  (V 0.5 ) V DSAT (V)k’(A/V 2 ) (V -1 ) NMOS x PMOS x (W/L) p 115 x (1.25 – 0.43 – 0.63/2) (W/L) n -30 x (1.25 – 0.4 – 1.0/2) =xx = 3.5 (W/L) p = 3.5 x 1.5 = 5.25 for a V M of 1.25V

EE415 VLSI Design Simulated Inverter V M (W/L) p /(W/L) n V M (V)  V M is relatively insensitive to variations in device ratio setting the ratio to 3, 2.5 and 2 gives V M ’s of 1.22V, 1.18V, and 1.13V  Increasing the width of the PMOS moves V M towards V DD.1 Note: x-axis is semilog ~3.4

EE415 VLSI Design Noise Margins Determining V IH and V IL V in V out V OH = V DD VMVM By definition, V IH and V IL are where dV out /dV in = -1 (= gain) V OL = GND A piece-wise linear approximation of VTC NM H = V DD - V IH NM L = V IL - GND Approximating: V IH = V M - V M /g V IL = V M + (V DD - V M )/g So high gain in the transition region is very desirable

EE415 VLSI Design CMOS Inverter VTC from Simulation V in (V) V out (V) 0.25um, (W/L) p /(W/L) n = 3.4 (W/L) n = 1.5 (min size) V DD = 2.5V V M  1.25V, g = V IL = 1.2V, V IH = 1.3V NM L = NM H = 1.2 (actual values are V IL = 1.03V, V IH = 1.45V NM L = 1.03V & NM H = 1.05V) Output resistance low-output = 2.4k  high-output = 3.3k 

EE415 VLSI Design Gain Determinates Gain is a function of the current slope in the saturation region, for V in = V M (1+r) g  (V M -V Tn -V DSATn /2)( n - p ) V in gain Determined by technology parameters, especially. Only designer influence through supply voltage and V M (transistor sizing).

EE415 VLSI Design Impact of Process Variation V in (V) V out (V) Nominal Good PMOS Bad NMOS Bad PMOS Good NMOS lPprocess variations (mostly) cause a shift in the switching threshold

EE415 VLSI Design Scaling the Supply Voltage V in (V) V out (V) Device threshold voltages are kept (virtually) constant V in (V) V out (V) Gain=-1 Device threshold voltages are kept (virtually) constant

EE415 VLSI Design Propagation Delay

EE415 VLSI Design Switch Model of Dynamic Behavior V DD RnRn V out CLCL V in = V DD V DD RpRp V out CLCL V in = 0 l Gate response time is determined by the time to charge C L through R p (discharge C L through R n )

EE415 VLSI Design What is the Inverter Driving?

EE415 VLSI Design CMOS Inverter Propagation Delay Approach 1

EE415 VLSI Design CMOS Inverter Propagation Delay Approach 2

EE415 VLSI Design CMOS Inverter: Transient Response How can the designer build a fast gate? t pHL = f(R on *C L ) Keep output capacitance, C L, small low fan-out keep interconnections short (floor-plan your layout!) Decrease on-resistance of transistor increase W/L ratio make good contacts (slight effect)

EE415 VLSI Design MOS Transistor Small Signal Model Define

EE415 VLSI Design Determining V IH and V IL V IH and V IL are based on derivative of VTC equal to -1

EE415 VLSI Design Transient Response t p = 0.69 C L (R eqn +R eqp )/2 ? t pHL t pLH

EE415 VLSI Design Inverter Transient Response V DD =2.5V 0.25  m W/L n = 1.5 W/L p = 4.5 R eqn = 13 k  (  1.5) R eqp = 31 k  (  4.5) t pHL = 36 psec t pLH = 29 psec so t p = 32.5 psec V in V out (V) t (sec) x tftf trtr t pHL t pLH From simulation: t pHL = 39.9 psec and t pLH = 31.7 psec

EE415 VLSI Design Delay as a function of V DD

EE415 VLSI Design Sizing Impacts on Delay The majority of improvement is obtained for S = 5. Sizing factors larger than 10 barely yields any extra gain (and cost significantly more area). S t p (sec) x for a fixed load self-loading effect (intrinsic capacitance dominates)

EE415 VLSI Design PMOS/NMOS Ratio Effects  of 2.4 (= 31 k  /13 k  ) gives symmetrical response  of 1.6 to 1.9 gives optimal performance  = (W/L p )/(W/L n ) t p (sec) x t pLH tptp t pHL

EE415 VLSI Design Input Signal Rise/Fall Time l The input signal changes gradually (and both PMOS and NMOS conduct for a brief time). l This affects the current available for charging/discharging C L and impacts propagation delay. t s (sec) t p (sec) x for a minimum-size inverter with a fan-out of a single gate l t p increases linearly with increasing input rise time, t r, once t r > t p l t r is due to the limited driving capability of the preceding gate

EE415 VLSI Design Inverter Sizing

EE415 VLSI Design CMOS Inverter Sizing V DD GND NMOS (2/.24 = 8/1) PMOS (4/.24 = 16/1) metal2 metal1 polysilicon In Out metal1-poly via metal2-metal1 via metal1-diff via pdiff ndiff

EE415 VLSI Design Inverter Delay Minimum length devices, L=0.25  m Assume that for W P = 2W N =2W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t pLH and fall t pHL delays Analyze as an RC network t pHL = (ln 2) R N C L t pLH = (ln 2) R P C L Delay (D): 2W2W W Load for the next stage:

EE415 VLSI Design Inverter with Load Load (C L ) Delay Assumptions: no load -> zero delay CLCL t p = k R W C L RWRW RWRW W unit = 1 k is a constant, equal to 0.69

EE415 VLSI Design Inverter with Load Load Delay C int CLCL Delay = kR W (C int + C L ) = kR W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) C N = C unit C P = 2C unit 2W2W W

EE415 VLSI Design Delay Formula C int =  C gin with   1 f = C L /C gin effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit   /1/1 0int ftCCCkRt pintLWp 

EE415 VLSI Design Inverter Chain l If C L is given »How should the inverters be sized? »How many stages are needed to minimize the delay? l Real goal is to minimize the delay through an inverter chain the delay of the j-th inverter stage is t p,j = t p0 (1 + C g,j+1 /(  C g,j )) = t p0 (1 + f j /  ) and t p = t p1 + t p t pN so t p =  t p,j = t p0  (1 + C g,j+1 /(  C g,j )) InOut CLCL C g,1 12N

EE415 VLSI Design Optimum Delay and Number of Stages When each stage is sized by f and has same fanout f: Minimum path delay Effective fanout of each stage:

EE415 VLSI Design Example C L = 8 C 1 In Out C1C1 1ff2f2 C L /C 1 has to be evenly distributed across N = 3 stages: Notice that in this case we may not have any time savings

EE415 VLSI Design l The optimum N is found by differentiating the minimum delay divided by the number of stages and setting the result to 0, l For  = 0 (ignoring self-loading) N = ln (F) and the effective-fan out becomes f = e = Optimal Number of Inverters l What is the optimal value for N given F (=f N ) ? »if the number of stages is too large, the intrinsic delay dominates »if the number of stages is too small, the effective fan- out dominates

EE415 VLSI Design Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f For  = 0, f = e, N = lnF

EE415 VLSI Design Optimum Effective Fan-Out l Choosing f larger than optimum has little effect on delay and reduces the number of stages (and area). »Common practice to use f = 4 (for  = 1) »Too many stages has a negative impact on delay  F op t f normalized delay

EE415 VLSI Design Example of Inverter (Buffer) Staging C L = 64 C g,1 C g,1 = 1 1 C L = 64 C g,1 C g,1 = C L = 64 C g,1 C g,1 = C L = 64 C g,1 C g,1 = N f t p

EE415 VLSI Design Impact of Buffer Staging for Large C L l Impressive speed-ups with optimized cascaded inverter chain for very large capacitive loads. F (  = 1) UnbufferedTwo Stage Chain Opt. Inverter Chain , ,00010,

EE415 VLSI Design Design Challenge l Keep signal rise times < gate propagation delays. »good for performance »good for power consumption l Keeping rise and fall times of the signals of approximately equal values is one of the major challenges in - slope engineering.

EE415 VLSI Design Power Dissipation

EE415 VLSI Design Power Dissipation Power consumption determines heat dissipation and energy consumption Power influences design decisions: packaging and cooling width of supply lines power-supply capacity # of transistors integrated on a single chip Power requirements make high density bipolar ICs impossible (feasibility, cost, reliability)

EE415 VLSI Design Power Dissipation Battery drain, cooling Supply-line sizing

EE415 VLSI Design Power Dissipation P peak = static power + dynamic power Dynamic power: (dis)charging capacitors temporary paths from VDD to VSS proportional to switching frequency Static power: static conductive paths between rails leakage increases with temperature

EE415 VLSI Design Power Dissipation Propagation delay is related to power consumption t p determined by speed of charge transfer fast charge transfer => fast gate fast gate => more power consumption Power-delay product (PDP) quality measure for switching device PDP = energy consumed /gate / switching event measured using ring oscillator

EE415 VLSI Design Power Dissipation Supply-line sizing Battery drain, cooling Energy consumed /gate /switching event

EE415 VLSI Design CMOS technology: No path exists between VDD and VSS in steady state No static power consumption! (ideally) Main reason why CMOS replaced NMOS NMOS technology: Has NMOS pull-up device that is always ON Creates voltage divider when pull-down is ON Power consumption limits # devices / chip CMOS Inverter: Steady State Response

EE415 VLSI Design Dynamic Power Dissipation VinVout C L Vdd Energy/transition = C L * V dd 2 Power = Energy/transition *f =C L * V dd 2 * f Need to reduce C L, V dd, andf to reduce power. Not a function of transistor sizes!

EE415 VLSI Design Modification for Circuits with Reduced Swing

EE415 VLSI Design Node Transition Activity and Power

EE415 VLSI Design Short Circuit Currents

EE415 VLSI Design How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t out_fall >> t in_rise, but can’t do this for cascade logic.

EE415 VLSI Design Minimizing Short-Circuit Power Vdd =1.5 Vdd =2.5 Vdd =3.3 Keep the input and output rise/fall times equal If V DD <V th +|V tp | then short circuit power can be eliminated

EE415 VLSI Design Leakage Sub-threshold currents rise exponentially with temperature.

EE415 VLSI Design Reverse-Biased Diode Leakage J S = pA/mm 2 at 25 deg C for 0.25mm CMOS J S doubles for every 9 deg C!

EE415 VLSI Design Subthreshold Leakage Component

EE415 VLSI Design Static Power Consumption

EE415 VLSI Design Principles for Power Reduction l Prime choice: Reduce voltage! »Supply voltage was reduced from 5 V to 1V over the years »25 time reduction of switching power l Reduce switching activity l Reduce physical capacitance »Device Sizing: for F=20 –f opt (energy)=3.53, f opt (performance)=4.47

EE415 VLSI Design Bad News l Voltage scaling has stopped as well »kT/q does not scale »Vth scaling has power consequences l If Vdd does not scale »Energy scales slowly Ed Nowak, IBM

EE415 VLSI Design Impact of Technology Scaling

EE415 VLSI Design Goals of Technology Scaling l Make things cheaper: »Want to sell more functions (transistors) per chip for the same money »Build same products cheaper, sell the same part for less money »Price of a transistor has to be reduced l But also want to be faster, smaller, lower power

EE415 VLSI Design Technology Scaling l Goals of scaling the dimensions by 30%: »Reduce gate delay by 30% (increase operating frequency by 43%) »Double transistor density »Reduce energy per transition by 65% (50% power 43% increase in frequency l Die size used to increase by 14% per generation l Technology generation spans 2-3 years

EE415 VLSI Design Technology Nodes Green – in use Orange - in development Blue –in plans

EE415 VLSI Design Technology Nodes Minimum Feature Size (nm)

EE415 VLSI Design Technology Nodes and Minimum Feature Sizes Minimum Feature Size (nm)

EE415 VLSI Design Leakage currents Currents [A/  m]

EE415 VLSI Design Supply voltage

EE415 VLSI Design ITRS Technology Roadmap Acceleration Continues

EE415 VLSI Design ITRS Technology Roadmap Acceleration Continues UWC136 Satellite Comm. LMDS SAT TV/WLAN RADAR IMT2000 Automotive Military CMOS SiGe-BICMOS III-V (InP)

EE415 VLSI Design Technology Scaling Minimum Feature Size

EE415 VLSI Design Technology Scaling Propagation Delay t p decreases by 13%/year 50% every 5 years!

EE415 VLSI Design Technology Scaling Models

EE415 VLSI Design Scaling Relationships for Long Channel Devices

EE415 VLSI Design Transistor Scaling (velocity-saturated devices)

EE415 VLSI Design Dilbert