Unit 12 Registers and Counters Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

22004/05/10Registers and Counters Outline 12.1Registers and Register Transfers 12.2Shift Registers 12.3Design of Binary Counters 12.4Counters for Other Sequences 12.5Counter Design Using S-R and J-K Flip-Flops Flip-Flops 12.6Derivation of Flip-Flop Input Equations -- Summary -- Summary

32004/05/10Registers and Counters Shift Registers A shift register Store binary data Store binary data The data can be shifted to the left or right The data can be shifted to the left or right Bits shifted out one end May be lost May be lost May be shifted back in the other end May be shifted back in the other end

42004/05/10Registers and Counters Right-Shift Register

52004/05/10Registers and Counters 8-Bit Serial-in, Serial-out Shift Register

62004/05/10Registers and Counters Timing Diagram for Shift Register

72004/05/10Registers and Counters Parallel-in, Parallel-out Right Shift Register

82004/05/10Registers and Counters Shift Register Operation

92004/05/10Registers and Counters Next-state Equations Q 3 + = Sh’ · L’ · Q 3 + Sh’ · L · D 3 + Sh · SI Q 2 + = Sh’ · L’ · Q 2 + Sh’ · L · D 2 + Sh · Q 2 Q 1 + = Sh’ · L’ · Q 1 + Sh’ · L · D 1 + Sh · Q 1 Q 0 + = Sh’ · L’ · Q 0 + Sh’ · L · D 0 + Sh · Q 0

102004/05/10Registers and Counters Timing Diagram for Shift Register

112004/05/10Registers and Counters Shift Register with Inverted Feedback

122004/05/10Registers and Counters Outline 12.1Registers and Register Transfers 12.2Shift Registers 12.3Design of Binary Counters 12.4Counters for Other Sequences 12.5Counter Design Using S-R and J-K Flip-Flops Flip-Flops 12.6Derivation of Flip-Flop Input Equations -- Summary -- Summary

132004/05/10Registers and Counters Binary Counters Synchronous counters Synchronized by a common clock pulse Synchronized by a common clock pulse State changes simultaneously State changes simultaneously Ripple counters The state change of one flip-flop triggers the next flip-flop in line. The state change of one flip-flop triggers the next flip-flop in line. Not discussed in this text Not discussed in this text

142004/05/10Registers and Counters Synchronous Binary Counter Using Three T flip-flops

152004/05/10Registers and Counters Synchronous Binary Counter The state of the counter is 011 Flip-flop C is in state 0 Flip-flop C is in state 0 Flip-flop B is in state 1 Flip-flop B is in state 1 Flip-flop A is in state 1 Flip-flop A is in state 1 Initially, assume that all flip-flops are set to 0 state.

162004/05/10Registers and Counters Synchronous Binary Counter Initially

172004/05/10Registers and Counters Synchronous Binary Counter 1st clock pulse

182004/05/10Registers and Counters Synchronous Binary Counter 2nd clock pulse

192004/05/10Registers and Counters Synchronous Binary Counter 3rd clock pulse

202004/05/10Registers and Counters Synchronous Binary Counter 4th clock pulse

212004/05/10Registers and Counters Synchronous Binary Counter The sequence of flip-flop states in CBA = 000, 001, 010, 011, 100, 101, 110, 111, 000, … The sequence repeats…. The sequence repeats….

222004/05/10Registers and Counters Synchronous Binary Counter Design the counter By inspection of the counting sequence By inspection of the counting sequence By a systematic procedure By a systematic procedure State table Karnaugh maps

232004/05/10Registers and Counters Synchronous Binary Counter

242004/05/10Registers and Counters Karnaugh Maps for Binary Counter

252004/05/10Registers and Counters Binary Counter with D Flip-Flops

262004/05/10Registers and Counters Karnaugh Maps for D Flip-Flops

272004/05/10Registers and Counters D Input Equations D A = A + = A ’ D B = B + = BA ’ + BA ’ = B  A D C = C + = C ’ BA + CB ’ + CA ’ = C ’ BA + C(BA) ’ = C ’ BA + C(BA) ’ = C  BA = C  BA

282004/05/10Registers and Counters An Up-Down Binary Counter U = 1, D = 0 The counter counts up. The counter counts up. U = 0, D = 1 The counter counts down. The counter counts down. U = 0, D = 0 The counter state does not change. The counter state does not change. U = 1, D = 1 Not allowed. Not allowed.

292004/05/10Registers and Counters An Up-Down Binary Counter

302004/05/10Registers and Counters An Up-Down Binary Counter

312004/05/10Registers and Counters Binary Up-Down Counter

322004/05/10Registers and Counters A Loadable Counter Two control signals Ld (load) and Ct (count) Ld (load) and Ct (count) Ld = 1, Ct = 0 Binary data is loaded into the counter Binary data is loaded into the counter Ld = 0, Ct = 1 The counter is incremented The counter is incremented Ld = Ct = 0 The counter holds its present value. The counter holds its present value. Ld = Ct = 1 Load overrides count Load overrides count

332004/05/10Registers and Counters Counter Operation

342004/05/10Registers and Counters Implementation