Introduction to Sequential Design

Types of Logic Circuits  Logic circuits can be: Combinational Logic Circuits-outputs depend only on current inputs Sequential Logic Circuits-outputs depends not only on current inputs but also on the past sequence of inputs

Sequential Circuit Models

Combinational Logic Delay Shortest delay Longest delay Longest timing delay = 5ns+5ns+5ns+5ns = 20ns Shortest timing delay = 5ns We will use the longest delay to represent the combinational logic (CL) delay, tcl

Combinational Logic (CL) Cloud Model Tcl=20ns

Memory

 We will add memory (or registers) to our logic circuits. This will allow us to design sequential circuits.

Registers  We will represent registers with the following block diagram Clock and reset are control signals Ns and ps are data signals

Sequential Systems Block Diagrams

Sequential Systems General Block Diagram Input Vector Output Vector Next State Present State Feedback Path CL= Combinational Logic Cloud Reg= D Registers Clock Reset

Sequential Systems General Block Diagram Input Vector Output Vector Next State Present State Feedback Path Clock Reset X is the input data vector Y is the output data vector

Sequential Systems Block Diagram Input Vector Output Vector Next State Present State Feedback Path Clock Reset Ns is the next state data vector Ps is the present state data vector

Sequential Systems Block Diagram Input Vector Output Vector Next State Present State Feedback Path Clock Reset Notice we have a feedback path which combines the ps data vector with the input vector to generate a new ns data vector.

Sequential Systems Block Diagram Input Vector Output Vector Next State Present State Feedback Path Clock Reset Mathematically, we say Or, ns is a function F of X and ps and Y is a function H of ps.

Example Circuit Schematic F LogicRegister H Logic (buffer) X input ns ps Block Diagram

Example Circuit Schematic F LogicRegister H Logic (buffer) X input ns ps State Equations

Finite State Machine (FSM) General Models

Moore FSM General Block Diagram Input Vector Output Vector Next State Present State Feedback Path CL= Combinational Logic Cloud Reg= D Registers Clock Reset

Moore FSM State Equations Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

Mealy FSM Block Diagram and State Equations Input Vector Output Vector Next State Present State Feedback Path Output Y is also a function of input X

Mealy-Moore FSM Block Diagram and State Equations Input Vector Next State Present State Mealy Outputs Moore Outputs

State Diagrams

State Bubble

State Bubble Example Unconditional Transition State name = S0 State value = 00 Y = 0 for this state Conditional Transition We leave this state if upn=1, We remain in this state if upn=0

Memory Devices

 Data Latch (D-latch)  Flip-flops (edge triggered) D-FF, D Register JK-FF T-FF

D-FF Positive Edge Triggered Block Diagram Symbol 4 inputs: D,Clk,Pre,Rst One output: Q D = Data Input Clk = Clock Input Pre = Preset Input Rst = Reset Input

D-FF Truth Table DClk dd100 dd011 d011 d Symbol Equation (rising clock) Truth Table

D-FF Truth Table DClk dd100 dd011 d011 d Symbol Equation (rising clock) Truth Table Pre= Preset Input (active low) Rst = Reset Input (active low) Highest priority

D-FF Truth Table DClk dd100 dd011 d011 d Symbol Equation (rising clock) Truth Table D = Data Input Clk = Clock input Qn = Register Output

FSM Examples

Example– 2-bit Up Counter  State Diagram Clock is implied

Example – 2-bit Up Counter  State Table psnsy S0S10 S21 S32 S03 S0 = 00 S1 = 01 S2 = 10 S3 = 11 Let Let S0 = reset state State Value Assignment Output Vector

Example – 2-bit Up Counter  Truth Table ps1ps0ns1ns0y1y

Example – 2-bit Up Counter  Excitation Equations

Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

Logic Diagram F Logic H Logic Reg Block Y Vector No X Vector in this Example No H Logic needed

Logic Diagram

Flash Animation

Example 3– 2-bit Down Counter  State Diagram Clock is implied

Example – 2-bit Down Counter  State Table psnsy S0S30 S23 S12 S01 S0 = 00 S1 = 01 S2 = 10 S3 = 11 Let Let S0 = reset state

Example – 2-bit Down Counter  Truth Table ps1ps0ns1ns0y1y

Example – 2-bit Down Counter  Excitation Equations

Recall Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

Logic Diagram F Logic H Logic Reg Block Y Vector No X Vector in this Example

Logic Diagram

Example 4 – 2-bit Up/Down Counter  State Diagram

Example – 2-bit Up/Down Counter  State Diagram Shorthand Notation

Example – 2-bit Up/Down Counter  State Table psns upn ns upn y S0S1S30 S1S2S01 S2S3S12 S3S0S23 S0 = 00 S1 = 01 S2 = 10 S3 = 11 Let Let S0 = reset state

Example – 2-bit Up/Down Counter  Truth Table upnps1ps0ns1ns0y1y

Example – 2-bit Up/Down Counter  Excitation Equations

Recall Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

Logic Diagram X Vector Y Vector F Logic H Logic Reg Block

Logic Diagram

Example 5– 3-bit Arbitrary Counter  Design a 3-bit arbitrary counter that will count in the following sequence 3,2,3,1,2,3 If a state is not used reset it to state zero. How may states do we have? How many registers do we need? How many bits do we need for Y?

Example 5– 3-bit Arbitrary Counter  State Diagram

Example – Arbitrary 3-bit Counter  State Table psnsy S0S13 S22 S33 S41 S02 S5S00 S6S00 S7S00 S0 = 000 S1 = 001 S2 = 010 S3 = 011 S4 = 100 S5 = 101 S6 = 110 S7 = 111 Let Let S0 = reset state Assign State Values

Develop Truth Table

Example – 2-bit Arbitrary Counter  Develop Excitation Equations -- F Logic

Develop Excitation Equations for Y Y1 Y0

Example – 2-bit Arbitrary Counter  Excitation Equations -- H Logic

Recall Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

Logic Circuit F H REGREG

Simulation

Example 5– 2-bit Up/Down Counter with Active Low Enable and Synchronous RESET (SRESET)  State Diagram Clock is implied

Example – 2-bit Up/Down Counter with Enable and SRESET  Functional Table srnenupnFunction 0dd Synchronous Reset (sreset) 11dHold 100Count Up 101Count Down Highest Level of PriorityLowest Level of Priority

State Table SrnEnup n ns 0ddS0 11dps 100ps+1 101ps -1

Truth Table (5 variables!!) Although, we could design this circuit directly from the truth table we will use design partitioning.

Moore FSM Architecture Input Vector Output Vector Next State Present State Feedback Path

Partitioned Design Note, with the partitioned design we can “reuse” already designed submodules to create the “new” design. SrnEnns 0dS0 11PS 10Count We have srn en

Top Level Block Diagram

UP/Down Logic Symbol Logic Circuit

Register Block Symbol Logic Circuit

2 Bit 4x1 Mux Symbol Circuit

1-bit 4x1 Mux Symbol Logic Circuit

1-bit 2x1 Mux Symbol Logic Circuit

Top Level Block Diagram

Simulation

Example 6 – FSM Controller State Diagram

Truth Table for NS Truth Table

Kmaps for NS1 and NS0 NS1 NS0

Truth Table and Equations for Y Truth Table By Inspection Recall, Moore FSM, so Y will Not be a function of T

Logic Circuit F H REGREG

Simulation

Memory Devices

Flip-Flops

D-FF Truth Table Qn follows D on Rising Edge of CLK DClk dd100 dd011 d011 d Symbol Equation (rising clock) Truth Table D = Data Input Clk = Clock input Qn = Register Output

T-FF (Toggle) Changes state on every tick of CLK TClk Dd100 Dd011 d011 d Symbol Equation (rising clock) Truth Table

SR-FF Set =>Qn=1 Reset=>Qn=0 SRClk ddd100 ddd011 dd011 dd ??? Symbol Equation (rising clock) Truth Table

JK-FF JKClk ddd100 ddd011 dd011 dd Symbol Equation (rising clock) Truth Table

Example: Design a JK-FF using only Logic and a D-FF JKClk ddd100 ddd011 dd011 dd Symbol Truth Table

Example State Diagram State Table Let s0=0 and s1=1

JK-FF Truth TableLogic Equations

Recall Moore FSM State Equations Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

JK Example Circuit Schematic F LogicD-Register H Logic (buffer) X input ns ps Block Diagram

JK Example Circuit Schematic Simulation

Latches

D-Latch Block Diagram Symbol 4 inputs: D,E,Pre,Rst One output: Q D = Data Input E = Enable Input Pre = Preset Input Rst = Reset Input

D-Latch Truth Table DE dd100 dd011 d Symbol Truth Table

D-Latch State Equations DE dd100 dd011 d Symbol Equation (level clock) Truth Table

SR-Latch State Equations SR dd100 dd ??? Symbol Equation (level clock) Truth Table

Example T-FF D-FF D-Latch

Simulation

Modular Sequential Logic

Shift Registers  Logic Design which manipulates the bit position of binary data by shifting it to the left or right.  Major application Serial Data to Parallel Data converters

Example  Design a three-bit shift register with the following functions S1S0Function 00 Synchronous Reset (sreset) 01Shift Right 10Shift Left 11No Shift

Partitioned Design

No Shift Equations and Circuit

Shift Left Equations and Circuit

Shift Right Equations and Circuit

Synchronous Reset Module

Registers

Total Design