Today’s Lecture Process model –initial & always statements Assignments –Continuous & procedural assignments Timing Control System tasks

Process Model 2 Basic statements in behavioral modeling initial statement & always statement All other procedural statements appear inside these statements Verilog is concurrent language unlike C; all the initial & always blocks run in parallel. All of them start at simulation time 0

Process Model (cont.) Initial block ( statement inside initial statement ) starts at time 0 and executes only once. If there are multiple blocks, they all start concurrently always block starts at time 0 and executes statements continuously in a loop, e.g. Examples: initial clock = 1’b’0; always # 10 clock = ~clock;

Assignments Continuous assignments assign values to nets (vector and scalar) –They are triggered whenever simulation causes the value of the right-hand side to change –Keyword “assign” e.g. assign out = in1 & in2; Procedural assignments drive values onto registers (vector and scalar) –They Occur within procedures such as always and initial –They are triggered when the flow of execution reaches them (like in C) –Blocking and Non-Blocking procedural assignments

Assignments (cont.) Procedural Assignments –Blocking assignment statement (= operator) acts much like in traditional programming languages. The whole statement is done before control passes on to the next statement –Nonblocking assignment statement (<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-hand sides at the end of the time unit

Assignments (cont.) Assignments Example: reg [0:7] A, B; Initial begin A = 3; #1 A = A + 1; B = A + 1; $display(“Blocking: A=%d B=%d:,A,B); A = 3; #1 A <= A + 1; B <= A + 1; end #1 $display(“Non-blocking: A=%d B=%d”,A,B); endmodule Ouput: Blocking: A=4 B=5 Non-blocking: A=4 B=4

Used when same functionality is required to be used at many places. Both must be defined in a module and are local to the module. They can have local variables, registers, time variable, integers, real but not wires. Tasks are used for the code that contains timing constructs or multiple outputs. Functions are used when the code is purely combinational, executes in 0 simulation time and has only one output. Tasks and Functions

A function can enable another function but not another task Functions always execute in zero simulation time Functions must not contain any delay, even or timing control statements Functions must have at least 1 input argument. can have more than 1 input Functions always return a single value. They can not have output or inout arguments A task can enable another tasks and functions Tasks may execute in non zero simulation time. Tasks may contain delay, event or timing control statements Tasks may have 0 or more arguments of type input, output, inout Tasks don ’ t return with a value but can paas multiple values through output & inout arguments Tasks and Functions (cont.)

task ; endtask To invoke a task: ( );

module tasks Tasks and Functions (cont.) task add; // task definition input a, b; // two input argument ports output c; // one output argument port reg R; // register declaration begin R = 1; if (a == b) c = 1 & R; else c = 0; end endtask initial begin: init1 reg p; add(1, 0, p); // invocation of task with 3 arguments $display("p= %b", p); end endmodule

function ; // Notice: no parameter list or ()s endfunction is the type of results passed back to the expression where the function was called. Inside the function, one must assign the function name a value. Tasks and Functions (cont.)

function [1:1] add2; // function definition input a, b; // two input argument ports reg R; // register declaration begin R = 1; if (a == b) add2 = 1 & R; else add2 = 0; end endfunction initial begin: init1 reg p; p = add2(1, 0); // invocation of function with 2 arguments $display("p= %b", p); end Module functions endmodule

Timing Control Verilog is a discrete event time simulator. If there is no timing control, simulation time does not advance. Simulated time can only progress by one of the following: –gate or wire delay, if specified – a delay control, introduced by the # symbol. –an event control, introduced by symbol. –the wait statement. The order of execution of events in the same clock time may not be predictable.

Delay Control (#) –Expression specifies the time duration between initially encountering the statement and when the statement actually executes. –Delay in Procedural Assignments Inter-Statement Delay Intra-Statement Delay –For example: Inter-Statement Delay #10 A = A + 1; Intra-Statement Delay A = #10 A + 1; Delay based Timing Control

Events –Change in the value of a register or net –Used to trigger execution of a statement or block (reactive behavior/reactivity) Types of Event-based timing control – Regular event control –Named event control –Event OR control –Level-sensitive timing control (wait statement) Event-Based Timing Control (cont.)

Regular event control ) –Events to specify: posedge sig: –Change of sig from any value to 1 or from 0 to any value negedge sig: –Change of sig from any value to 0 or from 1 to any value sig:Any chage in sig value Event-Based Timing Control (cont.)

Regular event control begin A = B&C; clock1) A = clock2) A = B&C; clock3) begin A = B&C; end

Named event control –You can declare (name) an event, and then trigger and recognize it. –Verilog keyword for declaration: event event event1; –Verilog symbol for triggering: -> ->event1 –Verilog symbol begin end Event-Based Timing Control (cont.)

Event OR control –Used when need to trigger a block upon occurrence of any of a set of events. –The list of the events: sensitivity list –Verilog keyword: or –Look at the handout Event OR control Example: ( reset or clock ) begin if ( reset ) q= 1’b0; else q= d; end

wait Statement –The wait statement allows a procedural statement or a block to be delayed until a condition becomes true. –The difference between the behavior of a wait statement and an event is that the wait statement is level sensitive clock); is triggered by a signal transition or is edge sensitive. –For Example: wait (A == 3) begin A = B&C; End Timing Control (cont.)

System tasks $display $finish $monitor $stop

System tasks (cont.) Standard tasks to do routine operations ; appear in form $ $display, $monitor ( similar to “printf” in C programming) Format strings : %d, %b,%s %h etc. $monitor is used to continuously monitors the values of variables and displays all parameters in list whenever value of any variable changes

System tasks (cont.) System Tasks contd. $stop is used to stop during simulation. ( suspend simulation) $finish is used to terminate simulation Compiler Directives : All are defined by using ‘ e.g. ‘define, ‘include { similar to C programming }