Chapter 5 Computer Organization ( 計算機組織 )

Distinguish between the three components of a computer hardware. List the functionality of each component. Understand memory addressing and calculate the number of bytes for a specified purpose. After reading this chapter, the reader should be able to: O BJECTIVES Distinguish between different types of memories. Understand how each input/output device works. Continued on the next slide

Understand the systems used to connect different components together. Understand the addressing system for input/output devices. Understand the program execution and machine cycles. O BJECTIVES (continued) Distinguish between programmed I/O, interrupt-driven I/O and direct memory access (DMA). Understand the two major architectures used to define the instruction sets of a computer: CISC and RISC.

Figure 5-1 Computer hardware (subsystems)

CENTRALPROCESSING UNIT (CPU) CENTRALPROCESSING 5.1

Figure 5-2 CPU

MAIN MEMORY 5.2

Table 5.1 Memory units Unit Unit kilobyte megabyte gigabyte terabyte petabyte exabyte Exact Number of bytes Exact Number of bytes bytes 2 20 bytes 2 30 bytes 2 40 bytes 2 50 bytes 2 60 bytes Approximation Approximation bytes 10 6 bytes 10 9 bytes bytes bytes bytes

Figure 5-3 Main memory

Memory addresses are defined using unsigned binary integers. Note:

Example 1 A computer has 32 MB (megabytes) of memory. How many bits are needed to address any single byte in memory? Solution The memory address space is 32 MB, or 2 25 (2 5 x 2 20 ). This means you need log or 25 bits, to address each byte.

Example 2 A computer has 128 MB of memory. Each word in this computer is 8 bytes. How many bits are needed to address any single word in memory? Solution The memory address space is 128 MB, which means However, each word is 8 (2 3 ) bytes, which means that you have 2 24 words. This means you need log or 24 bits, to address each word.

Memory Types RAM (Random access memory): –SRAM (Static RAM) (flip-flop gates) –DRAM (Dynamic RAM) ROM (Read only memory) –PROM (programmable) –EPROM (erasable programmable) –EEPROM (electronically erasable programmable)

A simple flip-flop circuit Set Reset

Setting the output of a flip-flop to 1

Setting the output of a flip-flop to 1 (continued)

Setting the output of a flip-flop to 1

Another way of constructing a flip-flop

Figure 5-4 Memory hierarchy

Figure 5-5 Cache

INPUT / OUTPUT 5.3

Figure 5-6 Physical layout of a magnetic disk

Figure 5-7 Surface organization of a disk

Figure 5-8 Mechanical configuration of a tape

Figure 5-9 Surface organization of a tape

Figure 5-10 Creation and use of CD-ROM

Table 5.2 CD-ROM speeds Speed x 2x 4x 6x 8x 12x 16x 24x 32x 40x Data Rate Data Rate ,600 bytes per second 307,200 bytes per second 614,400 bytes per second 921,600 bytes per second 1,228,800 bytes per second 1,843,200 bytes per second 2,457,600 bytes per second 3,688,400 bytes per second 4,915,200 bytes per second 6,144,000 bytes per second Approximation Approximation KB/s 300 KB/s 600 KB/s 900 KB/s 1.2 MB/s 1.8 MB/s 2.4 MB/s 3.6 MB/s 4.8 MB/s 6 MB/s

Figure 5-11 CD-ROM format

Figure 5-12 Making a CD-R

Figure 5-13 Making a CD-RW

Table 5.3 DVD capacities Feature Feature single-sided, single-layer single-sided, dual-layer double-sided, single-layer double-sided, dual-layer Capacity Capacity GB 8.5 GB 9.4 GB 17 GB

SUBSYSTEMINTERCONNECTIONSUBSYSTEMINTERCONNECTION 5.4

Figure 5-14 Connecting CPU and memory using three buses

Figure 5-15 Connecting I/O devices to the buses

Figure 5-16 SCSI controller (Small Computer System Interface) Daisy Chain

Figure 5-17 FireWire controller (IEEE 1394)

Figure 5-18 USB controller (Universal Serial Bus)

Figure 5-19 Isolated I/O addressing

Figure 5-20 Memory-mapped I/O addressing

PROGRAMEXECUTIONPROGRAMEXECUTION 5.5

Figure 5-21 Steps of a cycle

Figure 5-22 Contents of memory and register before execution

Figure 5-23.a Contents of memory and registers after each cycle

Figure 5-23.b Contents of memory and registers after each cycle

Figure 5-23.c Contents of memory and registers after each cycle

Figure 5-23.d Contents of memory and registers after each cycle

Figure 5-24 Programmed I/O

Figure 5-25 Interrupt-driven I/O

Figure 5-26 DMA connection to the general bus

Figure 5-27 DMA input/output

TWO DIFFERENT ARCHITECTURES ARCHITECTURES 5.6

Two different architectures CISC (Complex Instruction Set Computer) –Intel RISC (Reduced Instruction Set Computer) –PowerPC