ECE Team 3A Senior Capstone Lab Fall 2006 SUBSEA BLOW-OUT PREVENTER (BOP) CONTROL MODULE

Team 3a Name: Rob Warren Position: Project Manager

Team 3a Name: Mark Shook Position: Configuration Manager

Team 3a Name: Robert Fenton Position: Correspondent Officer

Team 3a Name: Duy Nguyen Position: Financial Officer

HYDRIL PRESSURE CONTROL Surface Surface Foreman Control Foreman Control Central Processing Central Processing Sub-Sea Sub-Sea Annular BOPs Annular BOPs Ram BOPs Ram BOPs Control Systems Control Systems

Requirements List of Critical Product Requirements List of Critical Product Requirements Operate in pressures up to 6700 psi. Operate in pressures up to 6700 psi. Operate two solenoids Operate two solenoids Monitor ram position (LVDT 0-10V) Monitor ram position (LVDT 0-10V) Calculate flow count ( GPM) via flow meter Calculate flow count ( GPM) via flow meter Communication to external host Communication to external host Capable of testing internal components Capable of testing internal components Modular Modular

OBJECTIVE RELIABLESUBMERSIBLESCALABLE

DESIGN PARADIGM Communications (TCP/IP) Communications (TCP/IP) Host to Sub-Sea Unit Host to Sub-Sea Unit Fiber Optics Fiber Optics Sub-Sea Intranet Sub-Sea Intranet Ethernet (802.3) Ethernet (802.3)

DESIGN PARADIGM Logic Logic Field Programmable Gate Array (FPGA) Field Programmable Gate Array (FPGA) Redundant Redundant Reliable Reliable Programmable Programmable

DESIGN PARADIGM Sensor Interface Sensor Interface Flow Meter Flow Meter Ram Position Sensor Ram Position Sensor Solenoid Interface Solenoid Interface Modified H-bridge Modified H-bridge Dual Direction Dual Direction Solenoid Test Solenoid Test H-bridge Test H-bridge Test

Host Power Interface (Solenoid) Main Logic (FPGA) Self Test A/D converter Flow Meter Solenoids LVDT HARDWARE SYSTEM

SOFTWARE SYSTEM COMMUNICATIONS LOGIC CORE LOGIC CORE LOGIC CORE BUFFER MAJORITY VOTER SOLENOID NET IFACE SOLENOID

SOFTWARE SYSTEM COMMUNICATIONS LOGIC CORE LOGIC CORE LOGIC CORE BUFFER NET IFACE FLOW METER ADC

SOFTWARE SYSTEM COMMUNICATIONS LOGIC CORE LOGIC CORE LOGIC CORE BUFFER NET IFACE LVDT ADC

Cond- itioning Ethernet Controller Microblaze Processor Solenoid Control Clocks ATD Power Solenoid- 60V LVDT -10V H-Bridge- 60V FPGA- 3.2V Mini module- 2.5V A/D converter 3.3V Mechanical External pressure (6700 psi) Size Inputs LVDT Flowmeter Network/ (802.3) Outputs Solenoid (1) (2 leads) Solenoid (2) (2 leads) Network/ (802.3) Power to sensors Functional Block Diagram

Solenoid Controller Solenoid 1 CPUIsolation Solenoid 2 High-Voltage Controller Isolated Sensor

TIMELINE Critical Points Critical Points Critical Design Review (CDR) Critical Design Review (CDR) Initial Assembly Initial Assembly Test Requirement Document (TRD) Test Requirement Document (TRD) Final Assembly Final Assembly Testing Testing Project Completion Date Project Completion Date

Critical Design Review Oct. 16 Parts Arrive- Initial Assembly Oct. 23 TRD Nov. 3 Final Assembly Nov. 10 Testing Nov. 13 Project Completion Dec. 01

WORK BREAKDOWN STRUCTURE Job List |Member Rob W Mark S Robert F Duy N Communication Protocol Development XX Research Power Requirements X Determine I/O Specifications X Locate Suitable Components XXX Develop Redundant Systems XXX Hardware Diagramming XX Software Diagramming XX SchematicsXX PrototypingXX Hardware Troubleshooting XX Final Assembly XX ProgrammingXXX Software Debugging XXX Test Procedure Development XX Product Testing/QA XX

COST OF MATERIALS ORDERED ItemPart Number (Mfg. Part #)Supplier WebsiteQtyPPUTotal FPGA BoardDS-KIT-3S400MM1em.avnet.com1$ FPGA Board w/BaseDS-KIT-3S400MM1-BASEem.avnet.com1$ A2D ConverterAD7705BNZdigikey.com3$8.33$24.99 Dual H-BridgeNJM2670D2digikey.com5$4.83$ mm 2x32 HeadersTMM S-Ddigikey.com6$7.52$45.12 Opto-IsolatorsHCPL-2530digikey.com6$2.10$12.60 Copper Plate BoardPC53-NDdigikey.com2$15.11$30.22 Total $707.08

Labor Hours Analysis Week Cum Bud Estimate at Complete Act Actual to date Delta %Percent Expended Weeks were slightly over allocated Weeks were slightly over allocated Weeks were under allocated Weeks were under allocated Overall Estimate at completion was under budgeted Overall Estimate at completion was under budgeted

Key features/Performance highlights Web user interface Web user interface Ability to fire both solenoids Ability to fire both solenoids Ease of interconnectivity/scalability Ease of interconnectivity/scalability Able to test the H-Bridge and solenoid coil with a trickle current. Able to test the H-Bridge and solenoid coil with a trickle current.

Tests Via TRD Feature Testing Feature Testing Send each software command from the host to the module and verify appropriate action / response Send each software command from the host to the module and verify appropriate action / response Redundancy Testing Redundancy Testing Disconnect both solenoids, instigate solenoid testing, and verify system failure report Disconnect both solenoids, instigate solenoid testing, and verify system failure report Individually disconnect each A/D converter, instigate a position measurement and verify individual system failure report (non-compliant subsystem) Individually disconnect each A/D converter, instigate a position measurement and verify individual system failure report (non-compliant subsystem) Power off 60V power supply, instigate solenoid controller test, and verify system failure report Power off 60V power supply, instigate solenoid controller test, and verify system failure report

Control Module

FPGA Board & Base

Solenoid Control/Test Module

Recommendations Communication Improvements Communication Improvements The Field Programmable Gate Array (FPGA) is using a Microblaze processor core which is running a sample webserver software package for Ethernet communication. This is a very limited server application and should be improved to allow for greater reliability and versatility. Currently the only means for accessing status information through the control module is by using any standard web browser. This can be very useful, though we recommend when improving the server software concurrently creating a host communication program. This program which would run on any PC or even server class machine could communicate with the control unit on a separate port than the web browser. This would allow for faster more data oriented communications, facilitating improved testing and allowing easier and more frequent collection of sub-sea data such as equipment operability status

Recommendations Redundancy The proposed design called for a highly redundant control unit, using three independent logic cores. These were designed, but not implemented due to time constraints. It is recommended to add these logic cores to the FPGA internal hardware. This Tri-Core technology will create greater redundancy and reliability by using the Microblaze processor solely as the communications driver. The design for this architecture can be located in Appendix 2.

Recommendations Additional Peripherals Additional Peripherals This design is highly scalable with over 100 unused I/O pins. These can be used to easily add the LVDT sensors through external A/D converters including redundant circuitry as well as the flow meter’s pulse train input. In addition, one control module could be configured to operate multiple pairs of solenoids by using an additional optocoupler / H- Bridge circuit for each added pair of solenoids. Multiple sensors could also be added to the control module through unused I/O pins.

SUMMARY Current System Current System Limited Environment Limited Environment Static Static Proposed System Proposed System Reliable Reliable Submersible Submersible Scalable Scalable

SUMMARY Straightforward Solution Straightforward Solution High Level Programming High Level Programming Completed by December 1 st Completed by December 1 st

HYDRIL “High Performance Products for Exploration and Production Worldwide”