Embedded Systems Design at Mentor

Platform Express Drag and Drop Design in Minutes IP Described In XML Databook s Simple System Diagrams represent complex designs. Consistent HW and SW Programmers View

Advanced IP Configuration Options n Statically Configured IP — Configuration options are generated automatically. n Dynamically Configured IP — Generated as part of the design creation/context process. n Platform Transforms — Auto-customization of IP for specific design contexts.

Creating The Design HDL n Choice of Verilog and VHDL. n Targeted for Modelsim and other simulators. n Auto-Generation of HDL bus infrastructure. — Platform Express is bus agnostic. — Proprietary and custom bus formats are easily supported.

Creating A Complete Verification SoC Environment n Seamless HW/SW Co-verification n Modelsim HDL Simulation n XRAY Embedded Debugger

Seamless Co-Verification n Enables software & hardware development in parallel n Removes software from the critical path n Reduces the risk of hardware iterations n Provides accurate analysis of system performance n Increases overall product quality n Increases visibility into your hardware SEAMLESS Co-Verification

Performance Profile Database System Profiler Balancing Performance & Detail with Seamless Coherent Memory Server SW Execution Code Debug HW Simulation Design Verification

VHDL/Verilog/SystemC Pin Wrapper BUS Interface Model (BIM) –Peripherals –Bus Cycle Timing –Controllers (DMA, MMU, Cache …) –Memory/BUS tracing/profiling Instruction Set Simulator (ISS) –Complete Instruction Set –Registers –Interrupt –Reset –Instruction Timing –Code Profiling Coherent Memory Server Memory Profiling Seamless Processor Support Packages n High-performance ISS models core functionality n Integrated high-level debugger, e.g. XRAY, RealView and Multi n Interface to ModelSim and all popular Verilog and VHDL simulators

Comprehensive CPU Support PowerPC 4xx PowerPC 603, 74x, 75x, 8xxx PowerQUICC I, II, III Oak, Teak, TeakLite, Palm 4K, 4KE, 5K, 20K, 24K SC1200, SC1400 Xtensa ARM7, ARM9 ARM10, ARM11, Cortex C6416, C64+, C55 RM70xx, RM79xx Models also available for Analog Devices, ARC, ETRI, Faraday, Fujitsu, Infineon, Intel, Lucent, Matsushita, NEC, Philips, Renesas, Samsung, ST, Toshiba, Xilinx ZSP400, ZSP500

Integrating the Software Domain with Assertion-based Verification Seamless ISS

Profiler Views Software Profile Bus Load Software Gantt Bus Delay Power Memory Heat Map

Profiler: Views aligned to show cause & effect

An Evolution of the “Traditional” Flow Paper Specification High Level Models Co-Verification HDL - RTL Design Design Debug Debug Verification Verification HDL - RTL Design Design Debug Debug Verification Verification Application BSP (drivers) Application RTOS Software Hardware SoftwareSoftwareHardware High Level Model Hardware System High Level Model Executable Specification System High Level Model Executable Specification Consistent Verification Requirements follow-up Virtual Prototype

Transaction Level Modeling n This is a methodology, also known as TLM, that defines new abstraction levels above the register. n It is itself made of several stages, which gradually abstract from hardware implementation constraints but still with a structured view of the design. n Its goal is to reduce the number of events and the amount of data that has to be treated during simulation. n This modeling method is built as a set of interfaces that define how models communicates. A Mem Generic CPU (B, C and ctrl) D TLM Channel A Mem Specific CPU - ISS (B, C and ctrl) D Bus Transactions TLM API ACD B TLMRTLAlgorithmic

The Performance of the Models AL Algorithmic Level (AL) Function Calls Functional description ≈ 10 MHz UML, Matlab, C/C++ PV Programmer View (PV) Generic Bus Architectural Memory Map ≈ 1 MHzSystemC PVT Programmer View + Timing (PVT) Bus specific Timing approximatio n ≈ 500 kHz SystemC CC Cycle Callable (CC) Word transfer Cycle accurate Clock Edges ≈ 10 kHzSystemC RTL Register Transfer Level (RTL) Signal and bits Cycle accurate ≈ 1 kHz VHDL, Verilog ACD B A Mem Generic CPU (B, C and ctrl) D TLM Channel A Mem Specific CPU - ISS (B, C and ctrl) D Bus Function Call Transaction Clock

Register Transfer Level Hardware Transaction Level Hardware virtual prototyping, high level verification environment, architecture refinement, performance verification Hardware Transaction Level Hardware virtual prototyping, high level verification environment, architecture refinement, performance verification System Exploration Level System executable specification, architecture exploration, HW/SW partitioning, mapping of functional list on HW/SW resources System Exploration Level System executable specification, architecture exploration, HW/SW partitioning, mapping of functional list on HW/SW resources Algorithmic Level Functional design and verification, exploration of the functional requirement list Algorithmic Level Functional design and verification, exploration of the functional requirement list Explore the feasibility of requirements Partition HW and SW - Define the architecture Finalize the specification Partition HW and SW - Define the architecture Finalize the specification Create a first prototype of the HW Create a verification infrastructure Create a first prototype of the HW Create a verification infrastructure Implement the hardware at register level In Summary “ESL Space” Uncommitted Systems Hardware Committed Functional Requirements Gates

Catapult C Synthesis – Algorithm to RTL Develop Algorithms using ANSI C++ No proprietary extension Focus on the functional intent Develop Algorithms using ANSI C++ No proprietary extension Focus on the functional intent Synthesize with Catapult C Explore the design space Find the optimal architecture Synthesize with Catapult C Explore the design space Find the optimal architecture Technology Files Technology Files Architectural Constraints Architectural Constraints Generate High Speed Models Verilog, VHDL, SystemC Accelerate system level verification Generate High Speed Models Verilog, VHDL, SystemC Accelerate system level verification Untimed TLM Timed TLM Cycle TLM Generate Target Optimized RTL Faster and better than hand-coded For ASIC, FPGA or FPGA prototyping of ASICs Generate Target Optimized RTL Faster and better than hand-coded For ASIC, FPGA or FPGA prototyping of ASICs Automatically Verify the RTL Generation of testbench infrastructure Seamlessly reuse original C++ test vectors Automatically Verify the RTL Generation of testbench infrastructure Seamlessly reuse original C++ test vectors

PerspectaPerspecta Perspecta n Modeling ‘components’ — Library builder and distributor n System Architecture — Assemble and modify design n Performance analysis — Throughput, bandwidth n Design validation — Functional and performance goals n HW/SW co-design — Full system integration n Verification — Hardware & software functional test PX for System Level MEM CPU Co-Proc MEMBridge Peri 1 Peri 2 Component Library Model Express my Algorithm switch( m_state ) { case RES_WAIT : if( rsp_fifo._get( rsp ) ) { send_resp( rsp ); } break; Software Debugging Environment System Analysis