Pipelined ADC Data Converters Pipelined ADCs Professor Y. Chiu

Slides:



Advertisements
Similar presentations
– 1 – Data ConvertersIntegration ADCProfessor Y. Chiu EECT 7327Fall 2012 Integration ADC.
Advertisements

Successive Approximation (SA) ADC
CMOS Comparator Data Converters Comparator Professor Y. Chiu
– 1 – Data ConvertersFlash ADCProfessor Y. Chiu EECT 7327Fall 2014 Flash ADC.
MB Page1Mihai Banu, July 2002 WCR #7 Nyquist rate ADC Main design motivation: Low Power Features: Pipeline arquitecture. Two interleaved ADCs with shared.
By: Ali Mesgarani Electrical and Computer Engineering University of Idaho 1.
Data Acquisition ET 228 Chapter
Quasi-Passive Cyclic DAC Gabor C. Temes School of EECS Oregon State University.
Mixed Signal Chip Design Lab Analog-to-Digital Converters Jaehyun Lim, Kyusun Choi Department of Computer Science and Engineering The Pennsylvania State.
18/05/2015 Calice meeting Prague Status Report on ADC LPC ILC Group.
A Low-Power 9-bit Pipelined CMOS ADC for the front-end electronics of the Silicon Tracking System Yuri Bocharov, Vladimir Butuzov, Dmitry Osipov, Andrey.
Design and Implementation a 8 bits Pipeline Analog to Digital Converter in The Technology 0.6 μm CMOS Process Eri Prasetyo.
NSoC 3DG Paper & Progress Report
– 1 – Data ConvertersSubranging ADCsProfessor Y. Chiu EECT 7327Fall 2014 Subranging ADC.
Algorithmic (Cyclic) ADC
– 1 – Data Converters Data Converter BasicsProfessor Y. Chiu EECT 7327Fall 2014 Data Converter Basics.
Jieh-Tsorng Wu National Chiao-Tung University Department of Electronics Engineering Team 1 Design Review – 2005/9/28 IEE 5644 Mixed-Signal IC Design and.
Introduction to Analog-to-Digital Converters
– 1 – Data ConvertersInterpolating and Folding ADCProfessor Y. Chiu EECT 7327Fall 2014 Interpolation.
CMOS VLSIAnalog DesignSlide 1 CMOS VLSI Analog Design.
– 1 – Data ConvertersDACProfessor Y. Chiu EECT 7327Fall 2014 DAC Architecture.
A Fast-Locked All-Digital Phase-Locked Loop for Dynamic Frequency Scaling Dian Huang Ying Qiao.
A 10 bit,100 MHz CMOS Analog- to-Digital Converter.
FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.
Time and Statistical Information Utilization in SAR ADCs
Energy Limits in A/D Converters
By Grégory Brillant Background calibration techniques for multistage pipelined ADCs with digital redundancy.
FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.
A 30-GS/sec Track and Hold Amplifier in 0.13-µm CMOS Technology
Analog to Digital conversion. Introduction  The process of converting an analog signal into an equivalent digital signal is known as Analog to Digital.
University of Tehran 1 Interface Design Transforms Omid Fatemi.
FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.
Guohe Yin, U-Fat Chio, He-Gong Wei, Sai-Weng Sin,
SIGMA-DELTA ADC SD16_A Sigma-Delta ADC Shruthi Sujendra.
A. Matsuzawa, Tokyo Tech. 1 Nano-scale CMOS and Low Voltage Analog to Digital Converter Design Challenges Akira Matsuzawa Tokyo Institute of.
Improvement of Accuracy in Pipelined ADC by methods of Calibration Techniques Presented by : Daniel Chung Course : ECE1352F Professor : Khoman Phang.
A 14-b 100-MS/s Pipelined ADC With a Merged SHA and First MDAC Byung-Geun Lee, Member, IEEE, Byung-Moo Min, Senior Member, IEEE, Gabriele Manganaro, Senior.
FE8113 ”High Speed Data Converters”. Part 2: Digital background calibration.
A 1V 14b Self-Timed Zero- Crossing-Based Incremental ΔΣ ADC[1] Class Presentation for Custom Implementation of DSP By Parinaz Naseri Spring
Data Acquisition ET 228 Chapter 15 Subjects Covered Analog to Digital Converter Characteristics Integrating ADCs Successive Approximation ADCs Flash ADCs.
High-Performance Analog-to-Digital Converters: Evolution and Trends
A 10b Ternary SAR (TSAR) ADC with Decision Time Quantization Based Redundancy Jon Guerber, Manideep Gande, Hariprasath Venkatram, Allen Waters, Un-Ku Moon.
1 A Cost-Efficient High-Speed 12- bit Pipeline ADC in 0.18-m Digital CMOS Terje Nortvedt Andersen, Bj ø rnar Hernes, Member, IEEE, Atle Briskemyr, Frode.
ISSCC 2008 Student Forum An 18 Gbps 2048-bit 10GBASE-T Ethernet LDPC Decoder Tinoosh Mohsenin Electrical & Computer Engineering, UC Davis
PREPARED BY V.SANDHIYA LECT/ ECE UNIT- 3 APPLICATIONS OF OP-AMP 1.
Erik Jonsson School of Engineering & Computer Science Redundant SAR ADC Architecture and Circuit Techniques for ATLAS LAr Phase-II Upgrade Ling Du 1, Hongda.
Pipelined ADC We propose two variants: low power and reliability optimized A. Gumenyuk, V. Shunkov, Y. Bocharov, A. Simakov.
Analog to Digital Converters
THERMAL NOISE ESTIMATION IN SWITCHED-CAPACITOR CIRCUITS
ECE 2799 Electrical and Computer Engineering Design ANALOG to DIGITAL CONVERSION Prof. Bitar Last Update:
Outline Abstract Introduction Bluetooth receiver architecture
Cache Pipelining with Partial Operand Knowledge Erika Gunadi and Mikko H. Lipasti Department of Electrical and Computer Engineering University of Wisconsin—Madison.
Reconfigurable Computing - Options in Circuit Design John Morris Chung-Ang University The University of Auckland ‘Iolanthe’ at 13 knots on Cockburn Sound,
Design of the 64-channel ASIC: update DEI - Politecnico di Bari and INFN - Sezione di Bari Meeting INSIDE, December 18, 2014, Roma Outline  Proposed solution.
Sill Torres: Pipelined SAR Pipelined SAR with Comparator-Based Switch-Capacitor Residue Amplification Pedro Henrique Köhler Marra Pinto and Frank Sill.
1 Progress report on the LPSC-Grenoble contribution in micro- electronics (ADC + DAC) J-Y. Hostachy, J. Bouvier, D. Dzahini, L. Galin-Martel, E. Lagorio,
Inexact and Approximate Circuits for Error Tolerant Applications IcySoc RTD 2013 Jérémy Schlachter, Vincent Camus, Christian Enz Ecole polytechnique fédérale.
0 /59 Nyquist Rate ADCs Dr. Hossein Shamsi ECE Dept, K.N. Toosi University of Technology.
Erik Jonsson School of Engineering & Computer Science High-Speed, High-Resolution, Radiation-Tolerant SAR ADC for Particle Physics Experiments Yuan Zhou.
Array Multiplier Haibin Wang Qiong Wu. Outlines Background & Motivation Principles Implementation & Simulation Advantages & Disadvantages Conclusions.
– 1 – Data ConvertersOversampling ADCProfessor Y. Chiu EECT 7327Fall 2014 Oversampling ADC.
Hongda Xu1, Yongda Cai1, Ling Du1, Datao Gong2, and Yun Chiu1
SAR ADC Tao Chen.
B.Sc. Thesis by Çağrı Gürleyük
Digital Error Correction
Hugo França-Santos - CERN
Pedro Henrique Köhler Marra Pinto and Frank Sill Torres
文化大學電機系2011年先進電機電子科技研討會 設計於深次微米CMOS製程之功率感知高速類比數位轉換積體電路 (Power-Aware High-Speed ADC in Deep Submicron CMOS)
Pingli Huang and Yun Chiu
Integration ADC Data Converters Integration ADC Professor Y. Chiu
Presentation transcript:

Pipelined ADC Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 Pipelined ADC

Pipelined ADC Architecture Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 Pipelined ADC Architecture A bucket brigade of algorithmic ADC w/ concurrent operation of all stages

A 1.5-Bit Stage 2X gain + 3-level DAC + subtraction all integrated Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 A 1.5-Bit Stage 2X gain + 3-level DAC + subtraction all integrated Digital redundancy relaxes the tolerance on CMP/RA offsets

Timing Diagram of Pipelining Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 Timing Diagram of Pipelining Two-phase nonoverlapping clock is typically used, with the coarse ADCs operating within the nonoverlapping times All pipelined stages operate simultaneously, increasing throughput at the cost of latency (what is the latency of pipeline? 1 T?)

1.5-Bit Decoding Scheme b 1 2 b-1 -1 +1 C2 +VR -VR Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 1.5-Bit Decoding Scheme b 1 2 b-1 -1 +1 C2 +VR -VR

A 2.5-Bit Stage Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 A 2.5-Bit Stage

2.5-Bit RA Transfer Curve 6 comparators + 7-level DAC are required Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 2.5-Bit RA Transfer Curve 6 comparators + 7-level DAC are required Max tolerance on comparator offset is ±VR/8

2.5-Bit Decoding Scheme b 1 2 3 4 5 6 b-3 -3 -2 -1 +1 +2 +3 b1 b2 b3 Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 2.5-Bit Decoding Scheme b 1 2 3 4 5 6 b-3 -3 -2 -1 +1 +2 +3 b1 b2 b3 C2 +VR -VR C3 C4 7-level DAC, 3×3×3 = 27 permutations of potential configurations → multiple choices of decoding schemes! Choose the scheme to minimize decoding effort, balance loading for reference lines, etc.

Pipelined ADC Features Limitations Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 Pipelined ADC Features Architecture complexity is proportional to the resolution N = Σnj Throughput is significantly improved relative to algorithmic or SAR Digital redundancy works the same way as algorithmic Inter-stage gain enables stage scaling to save power and area Limitations Typically 3 conversion operations are involved Sample-and-hold Sub-ADC comparison Sub-DAC and residue generation High-gain op-amps are required to produce residue signals with certain accuracy, which limits the conversion speed Long latency may be problematic for certain applications

No Stage Scaling Stage size/ power/area Input-referred kT/C noise Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 No Stage Scaling Stage size/ power/area Input-referred kT/C noise All stages identically sized – same capacitors, op-amps, comparators Later stages are clearly oversized due to inter-stage gains

Aggressive Stage Scaling Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 Aggressive Stage Scaling Stage size/ power/area Input-referred kT/C noise Stages sized such that the input-referred noises are identical Later stages are clearly downsized too aggressively

Optimum scaling lies in between the two extremes → S ≈ 2nj Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 Optimum Stage Scaling Stage size/ power/area Input-referred kT/C noise Optimum scaling lies in between the two extremes → S ≈ 2nj

Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 References S. H. Lewis and P. R. Gray, JSSC, pp. 954-961, issue 6, 1987. S. Sutarja and P. R. Gray, JSSC, pp. 1316-1323, issue 6, 1988. B.-S. Song et al., JSSC, pp. 1324-1333, issue 6, 1988. Y.-M. Lin, B. Kim, and P. R. Gray, JSSC, pp. 628-636, issue 4, 1991. S. H. Lewis et al., JSSC, pp. 351-358, issue 3, 1992. S.-H. Lee and B.-S. Song, JSSC, pp. 1679-1688, issue 12, 1992. A. N. Karanicolas, H.-S. Lee, and K. Barcrania, JSSC, pp. 1207-1215, issue 12, 1993. K. Sone et al., JSSC, pp. 1180-1186, issue 12, 1993. M. Yotsuyanagi et al., JSSC, pp. 292-300, issue 3, 1993. J. Wu, B. Leung, and S. Sutarja, ISCAS, 1994, pp. 461-464. T.-H. Shu, B.-S. Song, and K. Barcrania, JSSC, pp. 443-452, issue 4, 1995. T. B. Cho and P. R. Gray, JSSC, pp. 166-172, issue 3, 1995. E. G. Soenen and R. L. Geiger, TCAS2, pp. 143-153, issue 3, 1995. P. C. Yu and H.-S. Lee, JSSC, pp. 1854-1861, issue 12, 1996. D. W. Cline and P. R. Gray, JSSC, pp. 294-303, issue 3, 1996.

Data Converters Pipelined ADCs Professor Y. Chiu EECT 7327 Fall 2014 References M. K. Mayes and S. W. Chin, JSSC, pp. 1862-1872, issue 12, 1996. L. A. Singer and T. L. Brooks, VLSI, 1996, pp. 94-95. S.-U. Kwak, B.-S. Song, and K. Barcrania, JSSC, pp. 1866-1875, issue 12, 1997. K. Y. Kim, N. Kusayanagi, and A. A. Abidi, JSSC, pp. 302-311, issue 3, 1997. J. M. Ingino and B. A. Wooley, JSSC, pp. 1920-1931, issue 12, 1998. I. E. Opris et al., JSSC, pp. 1898-1903, issue 12, 1998. I. Mehr and L. A. Singer, JSSC, pp. 318-325, issue 3, 2000. L. A. Singer et al., ISSCC, 2000, pp. 38-39. W. Yang et al., JSSC, pp. 1931-1936, issue 12, 2001 B. Murmann and B. E. Boser, JSSC, pp. 2040-2050, issue 12, 2003. X. Wang, P. J. Hurst, and S. H. Lewis, CICC, 2003, pp. 409-412. J. Li and U.-K. Moon, CICC, 2003, pp. 413-416. Y. Chiu, P. R. Gray, and B. Nikolic, JSSC, pp. 2139-2151, issue 12, 2004. E. Siragusa and I. Galton, JSSC, pp. 2126-2138, issue 12, 2004. H.-C. Liu, Z.-M. Lee, and J.-T. Wu, ISSCC, 2004, pp. 454-455, 539.