©M.S. Engineering College, Bangalore 1 Interim Project Presentation “Title of the Project” Academic Guide:External Guide: Student NameReg. No.

©M.S. Engineering College, Bangalore 2 Aim of the Project To design PCI-E protocol and Verify the same with System Verilog VMM methodology.

©M.S. Engineering College, Bangalore 3 Project Objectives To review literature on PCI-Express and existing PCI/PCI-X protocols To review literature on VMM methodology and existing OVM and AVM methodologies To obtain the design specifications and suitable architecture for PCI-E Protocol To develop a Finite State Machine (FSM) for PCI-E and model the developed FSM in System Verilog To create effective VMM based Verification environment and verify PCI-E with the developed Verification environment

©M.S. Engineering College, Bangalore 4 Methods and Methodology Literature review on PCI-E and VMM Methodologies will be carried out by referring white papers, books, websites and related documents Design specifications for PCI-E will be arrived at based on reviewed literature Suitable architecture for PCI-E will be identified based on reviewed literature Finite State Machine will be developed for PCI-E based on design functionality Developed FSMs will be modeled individually in System Verilog to meet the specifications

©M.S. Engineering College, Bangalore 5 Methods and Methodology (cont..) SystemVerilog Assertions will be implemented in the modeled RTL appropriately Advantages and disadvantages of adding assertions to the design at the verification stage will be identified VMM based verification environment will be developed and the various components required for verification will be identified Methods will be adopted to increase the re-usability of Verification components Methodology developed will be implemented and the overall system will be verified with Constrained as well as Random test vectors Functional and Code coverage will be analyzed and methods will be adopted to improve the coverage

©M.S. Engineering College, Bangalore Introduction 6

©M.S. Engineering College, Bangalore Block Diagram 7

©M.S. Engineering College, Bangalore Need for this work 8

©M.S. Engineering College, Bangalore Design Details 9

©M.S. Engineering College, Bangalore Progress work 10

©M.S. Engineering College, Bangalore Progress work 11

©M.S. Engineering College, Bangalore 12 Place of work M. S. Engineering College Bangalore

©M.S. Engineering College, Bangalore 13 Project Schedule

©M.S. Engineering College, Bangalore 14 Resources Software Resources Synopsys VCS Literature Conference Papers Books Websites

©M.S. Engineering College, Bangalore 15 Literature Conference Papers 1.Salem Emara, Lawrence Sasaki and Wayn Wu, A Formal Approach for PCI Express Validation with IFV, CDN Live Renewei Wang and Zongyavo Wen, A Verification Environment for PCI-X BFM’s inVera, SNUG San Jose Fadi Saibi and Jing-Fan Zang, Integrating a PCI Express Digital IP Core into a Gigabit Ethrnet Controller, SNUG 2006

©M.S. Engineering College, Bangalore 16 Literature (contd.) 4. Rajeev Kumar, Advanced Switching based on PCI-E Architecture, ASI SIG Bus and Board Conference, January T. Rktimaki and J. Numi, Reconfigurable IP Blocks : a Survey, System- on-Chip, Proceedings International Symposium, pp , November Clifford E. Cummings, SystemVerilog - Is This The Merging of Verilog & VHDL?, SNUG Boston 2003

©M.S. Engineering College, Bangalore 17 Literature (contd.) Books 1.Ravi Budruk, Don Anderson and Tom Shanley, PCI Express System Architecture, Addison-Weley Pearson Edition, Stuart Sutherland, Simon Davidman and Peter Flake, System Verilog for Design, 2nd edition, Springer, Chris Spear, System Verilog for Verification, 2nd edition, Springer, Janick Bergeron, Writing Test benches Using SystemVerilog, 2nd edition, Springer, Janick Bergeron, VMM for System Verilog, 2nd edition, Springer, Andrew Piziali, Functional Verification Coverage Measurement and Analysis, Kluwer Academic Publications, 2004

©M.S. Engineering College, Bangalore 18 Literature (contd.) Websites 1.PCI Express Protocol Primer, systems.com/articles/id/?3931/, as accessed in Sept PCI Express Bus Description, as accessed in Sept Assertions in SystemVerilog:A Unified Language for More Efficient Verification, Tom Fitzpatrick, Synopsys Inc. f, as accessed in Aug 2008

©M.S. Engineering College, Bangalore 19 Benefits of the work Will it result into a publication? Yes Will it result into a product? No Will it be a solution to an existing problem of an industry? Yes Is it pursued for academic interest? Yes

©M.S. Engineering College, Bangalore 20 Thank You