M. S. Engineering College, Bangalore 1 Final Project Presentation Design and ASIC Implementation of Low-Power Viterbi Decoder for WLAN Applications Academic Guide 1:Academic Guide 2: Student NameUSN

M. S. Engineering College, Bangalore 2 Aim and Objectives of the Project AIM : To design and implement a low power Viterbi decoder for WLAN applications in ASIC using 130nm CMOS technology Objectives To review the literature on low power Viterbi decoder, WLAN and low power ASIC design algorithms and architecture. To arrive at design specifications of Viterbi decoder based on applications and to identify the suitable architecture. To develop a software reference model of the Viterbi decoder based on the derived specification To develop a hardware module of the Viterbi decoder based on the derived specification. To implement the Viterbi decoder using ASIC flow. To verify the completed design to meet the specifications.

M. S. Engineering College, Bangalore 3 Methods and Methodology The literature on algorithms and architecture for low power Viterbi decoder for wireless applications, WLAN and low power ASIC design is carried out by referring journals, books, websites and related documents. Design specification of low power Viterbi decoder for WLAN applications is formulated based on application and reviewed literature. Software reference model of the Viterbi decoder is developed. Suitable algorithm and architecture for low power Viterbi decoder for WLAN applications is identified as per the specifications and reviewed literature. Sub-modules of the low power Viterbi decoder is identified based on reviewed literature. Sub-modules of the low power Viterbi decoder is modeled in Verilog HDL and simulated using VCS.

M. S. Engineering College, Bangalore 4 Methods and Methodology (cont..) All the sub-modules is integrated and a test bench will be developed for the verification of the complete design using VCS. Synthesis and generation of the gate level net list for the low power Viterbi decoder design is done using Design Compiler. Timing Analysis of the design is done using Prime Time. Floor planning and power planning of the design is carried out using Astro. Placement and Routing of the design is done using Astro. Timing and power sign-off is carried out using Prime Time. GDSII for the low power Viterbi decoder design is generated.

M. S. Engineering College, Bangalore 5 Introduction Problem of digital communication – Transmit much data via a noisy channel – Detect and correct errors WLANs are flexible data communication systems implemented as the extensions or alternative to the wired LAN. The a uses OFDM technique a Receiver Block Diagram[1]

M. S. Engineering College, Bangalore 6 Introduction A convolutional coding is a class of error correcting codes which are widely used as channel coder in today’s digital communication systems. Viterbi Decoder is commonly used in decoding convolutional codes for wireless communication. VDs are widely used as forward error correction (FEC) blocks in many digital communication applications such as mobile phones, video and audio broadcasting receiver, modems and WLANs. Viterbi algorithm was devised by Andrew J. Viterbi in N-state Trellis Convolutional Encoder [9]

M. S. Engineering College, Bangalore 7 Literature Review (Summary) Basic Architecture of the VD has 3 major building blocks: BMU (branch metric Unit), ACSU (add-compare-select Unit), (SMU) Survivor Memory Unit 64 add-compare-select (ACS) operations There are no comparisons and selections to be made for the first 6 stages. Trace back length => 4 or 5 x K [4] The free distance D free = 10 for K=7 ACS unit consumes most power and area [1]. There are two ways of implementing the SMU: Register exchange and trace back method. Traceback method consumes less area and power but has high design complexity Basic Architecture of Viterbi decoder [1]

M. S. Engineering College, Bangalore 8 Literature Review Specifications ParameterSymbolValue Constraint Length K7 Code RateR1/2 Generator Polynomials GG0 = 171 8, G1 = Traceback Length TLTL 32 VD Decision Type --Hard SMU Type--Trace back Specifications of the Viterbi decoder are as given below:

M. S. Engineering College, Bangalore 9 Project Plan Derivation of Design Specifications Selection of Suitable Architecture Identification of Sub-modules H/W modeling using Verilog HDL and verification Dev. of Software Ref. model in Matlab Synthesis & Timing analysis Floor planning & Power Planning Placement & Routing Verification & Signoff Literature Review Implementation

M. S. Engineering College, Bangalore 10 Matlab Simulation Results Matlab Simulation results obtained are as shown below: `Input Data: Decoded DataOriginal Data Encoded data with noise

M. S. Engineering College, Bangalore 11 Design Procedure Block Diagram of Architecture of Viterbi Decoder BMUACS CTRLCTRL CLOCKCLOCK TBU MMU RAM Survivor Control & Clock Signals Bus DistanceLowestState Survivors Address Data Address Data RAM Metric PathMetric Address Code Reset Active Clock Decoded output

M. S. Engineering College, Bangalore 12 Design Procedure continued.. The BMU calculates the distance between the received symbols and code words on the branches. The ACS units perform comparison among candidate paths to determine survivors and compute the corresponding path metrics. Conventional ACSU architecture Low power ACSU(CSA) architecture

M. S. Engineering College, Bangalore 13 Design Procedure continued.. The memory management unit (MMU) governs the operations of SMU The clock and control unit are used to generate the clock and control signal respectively The trace back algorithm implemented could be described as follows : 1. At time t when TB_EN=1 get the lowest state from ACS. 2. From the survivor memory, get survivor value of those node. 3. Concatenate the lowest state and survivor bit and shift. 4. Traceback the shortest path to obtain the decoded output MMU Control Signals

M. S. Engineering College, Bangalore 14 Design Procedure continued.. Design of Hardware Model Hardware modeling of Viterbi Decoder is done in Verilog HDL using ModelSim. Design of sub-blocks – ACS unit, Branch metric unit and Survivor Memory unit. Design of Controller unit and Clock unit to provide control signals and clock signals for all the above sub-blocks. Integration of all the above sub-blocks to complete the Viterbi decoder block. Apart from the decoder design, a convolutional encoder was also designed for testing the viterbi decoder for different test cases

M. S. Engineering College, Bangalore 15 Hardware Design Flow Chart Synthesis, Optimization Static Time Analysis Floor planning and Power planning Place and Route Physical verification GDSII Generation Scan insertion Formality Timing met No Yes HDL coding

M. S. Engineering College, Bangalore 16 Design Procedure continued.. Schematic of Viterbi Decoder obtained in DC Decoded output Code Active Reset Clock Control Unit Clock Gen Unit ACSUBMUTBUMMU RAM

M. S. Engineering College, Bangalore 17 Design Procedure continued.. Test Bench Setup Viterbi Decoder Convolutional Encoder Testbench Input Data Code Word Decoded Output Input Data : Code word :

M. S. Engineering College, Bangalore 18 Simulation Results continued.. Encoder O/P & Decoder output VD O/P with no error at input Input Data: Encoder out : Decoded Output :

M. S. Engineering College, Bangalore 19 Simulation Results continued.. VD O/P with 4-bit error (near-by error) at input VD O/P with 4-bit error (Far-away error) at input Input Data : Code word : Decoded Output : Code word :

M. S. Engineering College, Bangalore 20 Simulation Results continued.. VD O/P with 6-bit error at input Input Data : Code word : Decoded Output :

M. S. Engineering College, Bangalore 21 Design Synthesis ParameterValue Technology130 nm LibrariesMVt TSMC CMOS No. of Cells3537 No. of Ports7 Area163974µm 2 Clock period20ns Total Power2.363mW The synthesis results are as shown below:

M. S. Engineering College, Bangalore 22 Physical Design Results Total number of cell instances: 9999 Total number of nets: Total number of ports: 9 Core Width = mm 2 Core Height = mm 2 CTSPlacement

M. S. Engineering College, Bangalore 23 Routing IRDrop Physical Design Results Power Report Total switching power = mW Total internal power = mW Total short-circuit power = mW Total leakage power = mW Total power = mW IR Drop Max voltage drop (mV) = (VDD)

M. S. Engineering College, Bangalore 24 My contribution A convolutional encoder was designed based on the a specification Reduced the total no ACS units from 64 to 4 ACS, thereby power reduction was achieved. An ACS unit was designed with a parallel architecture. Clock gating was used for reducing the power.

M. S. Engineering College, Bangalore 25 Conclusion Usage of CSA architecture lowers down hardware complexity as well as power dissipation to mW which is a reduction of 44% when compared to the reference design Reducing the number of ACS units to 4 from that used in other Viterbi Decoders reduces the area by 94% The width of the RAM influences the Data rate, the current width of 8 results in data rate of 1.56Mbps Changing the RAM size makes the design compatible for any constraint length with very few minor modifications The design not only considers the error correction capability, but also provides a power-efficient solution

M. S. Engineering College, Bangalore 26 Suggestions for future work Design of soft decision Viterbi decoder Design of a puncturing unit to achieve higher coding rates Implementation of parallel processing blocks to increase the throughput of the system

M. S. Engineering College, Bangalore 27 Literature Journals 1.C. C. Lin, Y. H. Shih, H. C. Chang and C. Y. Lee, “Design of a power reduction Viterbi decoder for WLAN application”, IEEE Trans. on Circuits and Systems-I, vol.52, no.6, pp.1148–1156, June D. A. El-dib and M. I. Elmasry, “Modified register exchange Viterbi decoder for low-power wireless communications”, IEEE Trans. Circuits Systems-I, vol.51, no.2, pp.371–378, February 2004

M. S. Engineering College, Bangalore 28 Literature (cont..) Conference Papers 3.Maharatna, K, Troya, A, Kristic, M and Grass E, “On the implementation of a Low-Power IEEE a compliant Viterbi Decoder”, in 19th VLSI Design Conference, Hyderabad, India, pp , April C.-C. Lin, C.-C. Wu, and C.-Y. Lee, “A low power and high speed Viterbi Decoder chip for WLAN applications”, in Proceedings of the 29th European Solid-State Circuits Conference (ESSCIRC'03), Lissabon, Portugal, pp.723–726, September 2003

M. S. Engineering College, Bangalore 29 Literature (cont..) Books 4.Bernard Sklar, “Digital Communications - Fundamentals and Applications”, 2 nd Edition, Pearson Education, ISBN: , Simon Haykin “Communication Systems”, John Wiley & Sons, 4 th Edition, ISBN: , Samir Palnitkar, “Verilog HDL – A Guide to Design and Synthesis”, Prentice Hall, ISBN: , 2003

M. S. Engineering College, Bangalore 30 Literature (cont..) Websites ( accessed as on Aug ) 7. (A Tutorial on Convolutional Coding with Viterbi Decoding) 8.Synopsys Online Documentation

M. S. Engineering College, Bangalore 31 Literature (cont..) 9. IEEE a WLAN physical layer specifications document 10. H.L. LOU, “Implementing the Viterbi Algorithm,” IEEE Signal processing Magazine, pp.42-52, Sept. 1995

M. S. Engineering College, Bangalore 32 Thank You

M. S. Engineering College, Bangalore