Micro transductors ’08 Low Power VLSI Design 1 Dr.-Ing. Frank Sill Department of Electrical Engineering, Federal University of Minas Gerais, Av. Antônio Carlos 6627, CEP: , Belo Horizonte (MG), Brazil

Copyright Sill, 2008 Micro transductors ‘08, Low Power 2 Agenda Recap Why do we worry about power? Metrics Where does power go in CMOS? How can we reduce the power dissipation? (1st part)

Copyright Sill, 2008 Micro transductors ‘08, Low Power 3 Recap: Transistor Geometrics polysilicon gate Gate length L Gate-width W t ox – thickness of oxide layer t ox Source Gate Drain Bulk

Copyright Sill, 2008 Micro transductors ‘08, Low Power 4 Recap: Logic Gates Task (e.g. calculation) Transfer into Logic Gates (Synthesis) Gate characteristics:  Delay  Power dissipation  more... Gates realized by transistors Y = A+B

Copyright Sill, 2008 Micro transductors ‘08, Low Power 5 Recap: CMOS Scheme PUN – Pull-up Network PDN – Pull-down Network VDD (supply voltage) GND (ground)

Copyright Sill, 2008 Micro transductors ‘08, Low Power 6 Transistor as Water-tap cont’d Voltage (Volt, V) Water pressure (bar) Current (Ampere, A) Water quantity per second (liter/s) - 0 Volt 1 Volt 0 Volt 1 Volt 0 Volt - 1 Volt Volt 1 Volt Source: Timmernann, 2007

Copyright Sill, 2008 Micro transductors ‘08, Low Power 7 Recap: RC-Delay Model Simple but effective delay model Use equivalent circuits for MOS transistors  Ideal switch  Transistor capacitances  ON resistance ( = when transistor is conducting (=ON)  channel between Drain to Source acts as resistor) Delay t ~ R*C X C out C P,gate C N,gate R N,DS C out C P,gate C N,gate

Copyright Sill, 2008 Micro transductors ‘08, Low Power 8 Sizing Increasing Width  Resistance get down  Increasing current  Decreasing delay  BUT  Capacitance increase too  Internal capacitances increase  + Output load of previous gates increases  Chain of Inverters: Optimum result (for speed) at equal fanout!

Copyright Sill, 2008 Micro transductors ‘08, Low Power 9 Trend: Performance Source: Moore, ISSCC 2003

Copyright Sill, 2008 Micro transductors ‘08, Low Power 10 Trend: Power Source: Moore, ISSCC 2003

Copyright Sill, 2008 Micro transductors ‘08, Low Power 11 Trend: Power Density Pentium® P Year Power Density (W/cm2) Hot Plate Nuclear Reactor Rocket Nozzle Sun’s Surface Prescott Pentium® Source: Moore, ISSCC 2003

Copyright Sill, 2008 Micro transductors ‘08, Low Power 12 Problems of High Power Dissipation Continuously increasing performance demands  Increasing power dissipation of technical devices  Today: power dissipation is a main problem High Power dissipation leads to:  High efforts for cooling  Increasing operational costs  Reduced reliability  High efforts for cooling  Increasing operational costs  Reduced reliability  Reduced time of operation  Higher weight (batteries)  Reduced mobility  Reduced time of operation  Higher weight (batteries)  Reduced mobility

Copyright Sill, 2008 Micro transductors ‘08, Low Power 13 Problems: Cooling

Copyright Sill, 2008 Micro transductors ‘08, Low Power 14 Problems: Cooling cont’d Solution?

Copyright Sill, 2008 Micro transductors ‘08, Low Power 15 Chip Power Density Distribution Power density is not uniformly distributed across the chip Silicon is not a good heat conductor Max junction temperature is determined by hot-spots  Impact on packaging, cooling Power Map On-Die Temperature

Copyright Sill, 2008 Micro transductors ‘08, Low Power 16 „The Internet is an Electricity Hog“ Energy for the internet in 2001 in Germany: 6.8 Bill. kWh = 1.4 % of total energy consumption  2.35 Bn. kWh for 17.3 Mill. Internet-PCs  1.91 Bn. for servers  1.67 Bn. for the network  0.87 Bn. for USV Rate of growth (at the moment): 36 % per year Prognosis: Bn. kWh  > 6 % total energy consumption  > 3 medium nuclear power plants World: 400 Mill. PCs  0.16 PW (P = Peta=10 15 ) Badische Zeitung, 2003

Copyright Sill, 2008 Micro transductors ‘08, Low Power 17 Dissipation in a Notebook Peripherals DiskDisplay WLAN Communication Ethernet Battery Power supply ASICs Memory programmable µPs or DSPs Processing DC-DC converter

Copyright Sill, 2008 Micro transductors ‘08, Low Power 18 Energy dissipation in a notebookEnergy dissipation a PDA Examples for Energy Dissipation

Copyright Sill, 2008 Micro transductors ‘08, Low Power 19 Battery Capacity Generalized Moore‘s Law Capacity of batteries 2% - 6% Increase per year (up to year 2000) Intel beats Varta Intel beats Varta Source: Timmernann, 2007

Copyright Sill, 2008 Micro transductors ‘08, Low Power 20 Current Progresses Batter. 20 kg Factor 4 in the last 10 years  still much too less

Copyright Sill, 2008 Micro transductors ‘08, Low Power 21 Metrics: Energy and Power Energy  Measured in Joules or kWh  “Measure of the ability of a system to do work or produce a change”  “No activity is possible without energy.” Power  Measured in Watts or kW  “Amount of energy required for a given unit of time.”  Average power Average amount of energy consumed per unit time Simplified to "power" in clear contexts  Instantaneous power Energy consumed if time unit goes to zero

Copyright Sill, 2008 Micro transductors ‘08, Low Power 22 Metrics: Energy and Power cont’d Instantaneous Electrical Power P(t)  P(t) = v(t) * i(t)  v(t): Potential difference (or voltage drop) across component  i(t): Current through component Electrical Energy  E = P(t) * t = v(t) * i(t) * t Electrical Energy in CMOS circuits  Energy = Power * Delay  Why?

Copyright Sill, 2008 Micro transductors ‘08, Low Power 23 CLCL Consumption in CMOS Voltage (Volt, V) Water pressure (bar) Current (Ampere, A) Water quantity per second (liter/s) EnergyAmount of Water Energy consumption is proportional to capacitive load! 0 1

Copyright Sill, 2008 Micro transductors ‘08, Low Power 24 CLCL Voltage (Volt, V) Water pressure (bar) Current (Ampere, A) Water quantity per second (liter/s) EnergyAmount of Water Consumption in CMOS cont’d Energy for calculation only consumed at 0→1 at output 0 1

Copyright Sill, 2008 Micro transductors ‘08, Low Power 25 Energy and Instantaneous Power CLCL CLCL INV1: High instantaneous Power (bigger width) INV2: Low instantaneous power t d1 t d2  Same Energy (C in ingnored)  INV1 is faster

Copyright Sill, 2008 Micro transductors ‘08, Low Power 26 Watts time Power is height of curve Watts time Energy is area under curve Approach 1 Approach 2 Approach 1 Metrics: Energy and Power cont’d Energy = Power * time for calculation = Power * Delay

Copyright Sill, 2008 Micro transductors ‘08, Low Power 27 Metrics: Energy and Power cont’d Energy dissipation  Determines battery life in hours  Sets packaging limits Peak power  Determines power ground wiring designs  Impacts signal noise margin and reliability analysis

Copyright Sill, 2008 Micro transductors ‘08, Low Power 28 Metrics: PDP and EDP Power-Delay Product  Power P, delay t p  Quality criterion PDP = P * t p [J] P and t p have some weight Two designs can have same PDP, even if t p = 1 year Energy-Delay Product  EDP = PDP * t p = P * t p 2  Delay t p has higher weight

Copyright Sill, 2008 Micro transductors ‘08, Low Power 29 Energy and Power Average Power direct proportional to Energy  In Following: Power means average power

Copyright Sill, 2008 Micro transductors ‘08, Low Power 30 Where Does Power Go in CMOS? Dynamic Power Consumption  Charging and Discharging Capacitors Short Circuit Currents  Short Circuit Path between Supply Rails during Switching Leakage  Leaking diodes and transistors

Copyright Sill, 2008 Micro transductors ‘08, Low Power 31 Dynamic Power Consumption P dyn = C L * V DD 2 * P 0  1 * f P 0  1 : probability for 0-to-1 switch of output f : clock frequency α : activity Data dependent - a function of switching activity! V in V out CLCL V DD f 0  1 = α * f

Copyright Sill, 2008 Micro transductors ‘08, Low Power 32 Short Circuit Power Consumption Finite slope of input signal  During switching: NMOS and PMOS transistors are conducting for short period of time (t sc )  Direct current path between VDD and GND P sc = V DD * I sc * (P 0  1 + P 1  0 ) V in V out CLCL I sc V DD GND t sc

Copyright Sill, 2008 Micro transductors ‘08, Low Power 33 Leakage Power Consumption Most important Leakage currents:  Subthreshold Leakage I sub  Gate Oxide Leakage I gate P leak = I leak * V DD ≈ (I sub + I gate )* V DD V DD GND CLCL I sub I gate SiO 2 Source Drain Gate I gate I sub L

Copyright Sill, 2008 Micro transductors ‘08, Low Power 34 P = α f C L V DD 2 + V DD I peak (P 0  1 + P 1  0 ) + V DD I leak Dynamic power (≈ % today and decreasing relatively) Short-circuit power (≈ 10 % today and decreasing absolutely) Leakage power (≈ 20 – 50 % today and increasing) Power Equations in CMOS

Copyright Sill, 2008 Micro transductors ‘08, Low Power 35 Levels of Optimization nach Massoud Pedram

Copyright Sill, 2008 Micro transductors ‘08, Low Power 36 Reducing V DD has a quadratic effect!  Has a negative effect on performance especially as V DD approaches 2V T Lowering C L  Improves performance as well  Keep transistors minimum size Reducing the switching activity, f 0  1 = P 0  1 * f  A function of signal statistics and clock rate  Impacted by logic and architecture design decisions Lowering Dynamic Power

Copyright Sill, 2008 Micro transductors ‘08, Low Power 37 Transistor Sizing for Power Minimization Larger sized devices: only useful only when interconnects dominate Minimum sized devices: usually optimal for low-power Small W’s Large W’s Higher Voltage Lower Voltage Lower Capacitance Higher Capacitance Source: Timmernann, 2007 To keep performance

Copyright Sill, 2008 Micro transductors ‘08, Low Power 38 Logic Style and Power Consumption Voltage decreases: Power-delay product improves Best logic style minimizes power-delay for a given delay constraint  New Logic style can reduced Power dissipation (if possible / available !) Source: Timmernann, 2007

Copyright Sill, 2008 Micro transductors ‘08, Low Power 39 Transistor Reordering Logically equivalent CMOS gates may not have identical energy/delay characteristics

Copyright Sill, 2008 Micro transductors ‘08, Low Power 40 Transistor Reordering cont’d Normalized P dyn Activity (transitions / s)(A)(B)(C)(D)max. savings A a1 = 10 K (1)A a2 = 100 K % A b = 1 M A a1 = 1 M (2)A a2 = 100 K % A b = 10 K  For given logic function and activity: Signal with highest activity → closest to output to reduce charging/discharging internal nodes

Copyright Sill, 2008 Micro transductors ‘08, Low Power 41 Impact of rise/fall times on short-circuit currents Source: Timmernann, 2007

Copyright Sill, 2008 Micro transductors ‘08, Low Power 42 I sc as a Function of C L I sc (A) time (sec) x x C L = 20 fF C L = 100 fF C L = 500 fF 500 ps input slope  At small load capacitance C L  large I sc  But: large C L increases P dyn  2 nd Possibility: Minimization of short circuit dissipation by matching the rise/fall times of input and output signals  Slope engineering

Copyright Sill, 2008 Micro transductors ‘08, Low Power 43 Example: Static 2 Input NOR Gate P A=1 = 1/2 P B=1 = 1/2 P Out=0 = 3/4 P Out=1 = 1/4 P 0→1 = P Out=0 * P Out=1 = 3/4 * 1/4 = 3/16 Then: Transition Probabilities for CMOS Gates ABOut Truth table of NOR2 gate If A and B with same input signal probability: C eff = P 0→1 * C L = 3/16 * C L Source: Timmernann, 2007

Copyright Sill, 2008 Micro transductors ‘08, Low Power 44 P 0  1 = P out=0 * P out=1 NOR(1 - (1 - P A )(1 - P B )) * (1 - P A )(1 - P B ) OR(1 - P A )(1 - P B ) * (1 - (1 - P A )(1 - P B )) NANDP A P B * (1 - P A P B ) AND(1 - P A P B ) * P A P B XOR(1 - (P A + P B - 2P A P B )) * (P A + P B - 2P A P B ) Transition Probabilities cont’d A and B with different input signal probability: P A and P B : Probability that input is 1 P 1 : Probability that output is 1 Switching activity in CMOS circuits: P 0  1 = P 0 * P 1 For 2-Input NOR: P 1 = (1-P A )(1-P B ) Thus: P 0  1 = (1-P 1 )*P 1 = [1-(1-P A )(1-P B )]*[(1-P A )][1-P B ] (see next slide)

Copyright Sill, 2008 Micro transductors ‘08, Low Power 45 Transition Probability of NOR2 Gate as a Function of Input Probabilities Transition Probabilities cont’d Probability of input signals → high influence on P 0  1 Source: Timmernann, 2007

Copyright Sill, 2008 Micro transductors ‘08, Low Power 46 Logic Restructuring  Chain implementation has a lower overall switching activity than tree implementation for random inputs  BUT: Ignores glitching effects  Logic restructuring: changing the topology of a logic network to reduce transitions A B C D F A B C DZ F W X Y 0.5 (1-0.25)*0.25 = 3/ /64 = /256 3/16 3/16 = /256 AND: P 0  1 = P 0 * P 1 = (1 - P A P B ) * P A P B Source: Timmernann, 2007

Copyright Sill, 2008 Micro transductors ‘08, Low Power 47 Input Ordering Beneficial: postponing introduction of signals with a high transition rate (signals with signal probability close to 0.5) A B C X F B C A X F (1-0.5x0.2)*(0.5x0.2)=0.09 (1-0.2x0.1)*(0.2x0.1)= Source: Timmernann, 2007 AND: P 0  1 = (1 - P A P B ) * P A P B

Copyright Sill, 2008 Micro transductors ‘08, Low Power 48 ABC X Z Unit Delay A B X Z C Glitching

Copyright Sill, 2008 Micro transductors ‘08, Low Power 49 Example 1: Chain of NAND Gates V DD / 2

Copyright Sill, 2008 Micro transductors ‘08, Low Power 50 Example 2: Adder Circuit V DD / 2

Copyright Sill, 2008 Micro transductors ‘08, Low Power 51 How to Cope with Glitching? F 1 F 2 F F 1 F 3 F Equalize Lengths of Timing Paths Through Design