ريزپردازنده ها Microprocessors Spring 2005

Books Author: Burry B. Brey Translator: Hossein Nia The Z80 Microprocessor , Hardware , Software programming & interfacing Author: Burry B. Brey Translator: Hossein Nia Publisher: Astane Ghodse Razavi(Beh Nashr

Books Microcompiuter and Microprocessor : the 8080 , 8085 , Z-80 Programming , interfacing and trubleshooting Publisher: Nass Pub.Date: 1381 Edition Turn: 3 ISBN: 964-6264-43-4-3 Pages: 719 Author: John E . UffenbeckTranslator: Mahmmod Dayani

Books The 80x86 IBM PC and compatible computers (Design and interfacing of the IBM PC PS and compatible) Publisher: Baghani Pub.Date: 1379 Edition Turn: 2 ISBN: 964-91532-3-3 Pages: 760 Author: Mohammad Ali . Mazidi Janice Gillispie . MazidiTranslator: Dr. Sepidnam

Books Microcontroller 8051 Publisher: Baghani Pub.Date: 1380 ISBN: 964-7343-00-0 Pages: 380 Author: Mohammad ali Mazidi Jonis Glispi MazidiTranslator: Dr. Sepidnam

Books The 8051 Microcontroller Publisher: Baghani Pub.Date: 1380 Publishing Turn: 5 Edition Turn: 3 ISBN: 964-91532-2-5 Pages: 383 Author: Iscott Makenzi Translator: Rezaei Nia ,Darbandi Azar

Intruduction Microprocessor (uP)(MPU) Micro-computer (u-Computer) A uP is a CPU on a single chip. Components of CPU ALU, instruction decoder, registers, bus control circuit, etc. Micro-computer (u-Computer) small computer uP + peripheral I/O + memory specifically for data acquisition and control applications Microcontroller (uC) u-Computer on a single chip of silicon

uP vs. uC A uP A uC only is a single-chip CPU bus is available RAM capacity, num of port is seletable RAM is larger than ROM (usually) A uC contains a CPU and RAM,ROM ,Prepherals, I/O port in a single IC internal hardware is fixed Communicate by port ROM is larger than RAM (usually) Small power consumption Single chip, small board Implementation is easy Low cost

uP vs. uC – cont. Applications uCs are suitable to control of I/O devices in designs requiring a minimum component uPs are suitable to processing information in computer systems.

uP vs. uC – cont. uC is easy to use and design. Only single chip can be a complete system interfacing to other devices, for example, motors, displays, sensors, and communicate with PC. In contrast, similar system that builds from uP would require a lot of additional units, such as RAM, UART, I/O , TIMER and etc.

uC is a Reusable Hardware Logic circuit provides limited function for one single design. In order to change circuit’s functionality, we need to redesign the circuits. uC can reprogram and change functionality of every port, input to output or digital to analog on the fly.

uCs Many uCs are existing right now. 8051, 68HC11, MSP430, ARM series, and etc. We may widely divide it with how it is designed RISC/CISC architecture. What is the main difference between RISC/CISC? Does it make any difference to our application?

The Microprocessor (MPU) The uP is the ‘brain of the microcomputer’ Is a single chip which is capable of processing data controlling all of the components which make up the microcomputer system µP used to sequence executions of instructions that is in memory uP Fetch , Decode , and Execute the instruction The internal architecture of the microprocessor is complex.

The Microprocessor (MPU) microprocessor (MPU) typically contains Registers: Temporary storage locations for program instruction or data. The Arithmetic Logic unit (ALU): This part of the MPU performs both arithmetic and logical operations Timing and Control Circuits: that keep all of the other parts of system (Regs, ALU, memory & I/O) working together in the right time sequence

Microcomputers All Microcomputers consist of (at least) : 1. Microprocessor Unit (MPU) 2. Program Memory (ROM) 3. Data Memory (RAM) 4. Input / Output ports 5. Bus System (and Software) MPU is the brain of microcomputer

Microcomputers

The Input/Output (I/O) System I/O is the link between the MPU and the outside world. An input port is a circuit through which an external device can send signals (data?) to the MPU. An output port is a circuit that allows the MPU to send signals (data?) to external devices. I/O ports connect both digital and analogue devices by DAC and ADC

Bus A Bus is a common communications pathway used to carry information between the various elements of a computer system The term BUS refers to a group of wires or conduction tracks on a printed circuit board (PCB) though which binary information is transferred from one part of the microcomputer to another The individual subsystems of the digital computer are connected through an interconnecting BUS system.

Bus There are three main bus groups ADDRESS BUS DATA BUS CONTROL BUS

Data Bus The Data Bus carries the data which is transferred throughout the system. ( bi-directional) Examples of data transfers Program instructions being read from memory into MPU. Data being sent from MPU to I/O port Data being read from I/O port going to MPU Results from MPU sent to Memory These are called read and write operations

Address Bus An address is a binary number that identifies a specific memory storage location or I/O port involved in a data transfer The Address Bus is used to transmit the address of the location to the memory or the I/O port. The Address Bus is unidirectional ( one way ): addresses are always issued by the MPU.

Control Bus The Control Bus: is another group of signals whose functions are to provide synchronization ( timing control ) between the MPU and the other system components. Control signals are unidirectional, and are mainly outputs from the MPU. Example Control signals RD: read signal asserted to read data into MPU WR: write signal asserted to write data from MPU

Main memory The duties of the memory are : Main memory Types To store programs To provide data to the MPU on request To accept result from the MPU for storage Main memory Types ROM : read only memory. Contains program (Firmware). does not lose its contents when power is removed (Non-volatile) RAM: random access memory (read/write memory) used as variable data, loses contents when power is removed volatile. When power up will contain random data values

Read-Only Memory uP can read instructions from ROM quickly Cannot write new data to the ROM ROM remembers the data, even after power cycled Typically, when the power is turned on, the microprocessor will start fetching instructions from the still-remembered program in ROM (bootstrap ) On a PC, the ROM is called the BIOS (Basic Input/Output System). When the microprocessor starts, it begins executing instructions it finds in the BIOS. The BIOS instructions do things like test the hardware in the machine, and then it goes to the hard disk to fetch the boot sector. This boot sector is another small program, and the BIOS stores it in RAM after reading it off the disk. The microprocessor then begins executing the boot sector's instructions from RAM. The boot sector program will tell the microprocessor to fetch something else from the hard disk into RAM, which the microprocessor then executes, and so on. This is how the microprocessor loads and executes the entire operating system

Available ROMs Masked ROM or just ROM PROM or programmable ROM(once only) EPROM (erasable via ultraviolet light) Flash (can be erased and re-written about 10000 times, usually must write a whole block not just 1 byte or 2 bytes, slow writing, fast reading) EEPROM (electrically erasable read-only memory, also known as EEROM—both reading and writing are very slow but can program millions of times…useless for storing a program but good for say configuration information.

ROM ROM Capacity : PROM EEPROM : Output Enable connect to RD of uP m+1 bit Address n+1 bit Data Am Dn ROM PROM EEPROM Capacity : : Output Enable connect to RD of uP : Chip Enable to Address decoder

Timing Diagram for a Typical ROM A0-Am D0-Dn OE falls to data valid Addr valid to data valid

27XX EPROM PGM and VPP are used to programming 64 kbit 8 kbyte 16 kbit

27XXX EPROM 128 kbit 16 kbyte 256 kbit 32 kbyte 512 kbit 64 kbyte

28XX E2PROM 16 kbit 64 kbit 1026 kbit 4096 kbit 256 kbit 2 kbyte

RAM (Random Access Memory) The uP can read the data from RAM quickly, The uP can write new data quickly to RAM RAM forgets its data if power is turned off Two type of is available : Static RAM(SRAM): ff base, fast, expensive, low cap/vol, applied for cache , no refresh Dynamic RAM (DRAM): cap base, slow , low cost high capacity/volume , applied for main memory(pc) need refresh. RAM stands for random-access memory. RAM contains bytes of information, and the microprocessor can read or write to those bytes depending on whether the RD or WR line is signaled. One problem with today's RAM chips is that they forget everything once the power goes off. That is why the computer needs ROM

RAM(Static) Capacity : RAM Data bus is Bidirectional : Read signal m+1 bit Address n+1 bit Data Am Dn Capacity : RAM Data bus is Bidirectional : Read signal connect to MemRD of uP : Write signal connect to MemWR of uP : Chip Select to Address decoder

Session 2 Microprocessors History Data width 8086 vs 8088 8086 pin description Z80 Pin description

Microprocessors Microprocessors come in all kinds of varieties from the very simple to the very complex Depend on data bus and register and ALU width uP could be 4-bit , 8-bit , 16-bit, 32-bit , 64-bit We will discuss two sample of it Z80 as an 8-bit uP and 8086/88 as an 16-bit uP All uPs have the address bus the data bus RD, WR, CLK , RST, INT, . . .

History Company 4 bit 8 bit 16 bit 32 bit 64 bit intel 4004 4040 8008 8080 8085 8088/6 80186 80286 80386 80486 80860 pentium zilog Z80 Z8000 Z8001 Z8002 Motorola 6800 6802 6809 68006 68008 68010 68020 68030 68040

Internal and External Bus Internal bus is a pathway for data transfer between registers and ALU in the uPs External bus is available externally to connect to RAM, ROM and I/O Int. and Ext. Bus width may be different For example In 8088 Int. Bus is 16-bit , Ext. bus is 8-bit In 8086 Int. Bus is 16-bit , Ext. bus is 16-bit Data Width is the width of the ALU. An 8-bit ALU can add/subtract/multiply/etc. two 8-bit numbers, while a 32-bit ALU can manipulate 32-bit numbers. An 8-bit ALU would have to execute four instructions to add two 32-bit numbers, while a 32-bit ALU can do it in one instruction. In many cases, the external data bus is the same width as the ALU, but not always. The 8088 had a 16-bit ALU and an 8-bit bus, while the modern Pentiums fetch data 64 bits at a time for their 32-bit ALUs.

8086 vs 8088 Only external bus of 8088 is 8_bit 8088 8086 8_bit Data Bus 20_bit Address 16_bit Data Bus 20_bit Address 8086 8088

8086 Pin Assignment

8086 Pin Description Vcc (pin 40) : Power Gnd (pin 1 and 20) : Ground AD0..AD7 , A8..A15 , A19/S6, A18/S5, A17/S4, A16/S3 : 20 -bit Address Bus MN/MX’ (input) : Indicates Operating mode READY (input , Active High) : take uP to wait state CLK (input) : Provides basic timing for the processor RESET (input, Active High) : At least 4 clock cycles Causes the uP immediately terminate its present activity. TEST’ (input , Active Low) : Connect this to HIGH HOLD (input , Active High) : Connect this to LOW HLDA (output , Active High) : Hold Ack INTR (input , Active High) : Interrupt request INTA’ (output , Active Low) : Interrupt Acknowledge NMI (input , Active High) : Non-maskable interrupt

8086 Pin Description DEN’ (output) : Data Enable. It is LOW when processor wants to receive data or processor is giving out data (to74245) DT/R’ (output) : Data Transmit/Receive. When High, data from uP to memory When Low, data is from memory to uP (to74245 dir) IO/M’ (output) : If High uP access I/O Device. If Low uP access memory RD’ (output) : When Low, uP is performing a read operation WR’ (output) : When Low, uP is performing a write operation ALE (output) : Address Latch Enable , Active High Provided by uP to latch address When HIGH, uP is using AD0..AD7, A19/S6, A18/S5, A17/S4, A16/S3 as address lines

Z80 CPU Pin Assignment

Z80 Pin Description A15-A0 : D7-D0 : RD: WR: Address bus (output, active high, 3-state). Used for accessing the memory and I/O ports During the refresh cycle the I is put on this bus. D7-D0 : Data Bus (input/output, active high, 3-state). Used for data exchanges with memory, I/O and interrupts. RD: Read (output, active Low, 3-state) indicates that the CPU wants to read data from memory or I/O WR: Write (output, active Low, 3-state) indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O location.

Z80 Pin Description MREQ IORQ M1 RFSH Memory Request (output, active Low, 3-state). Indicates memory read/write operation. See M1 IORQ Input/Output Request(output,active Low,3-state) Indicates I/O read/write operation. See M1 M1 Machine Cycle One (output, active Low). Together with MREQ indicates opcode fetch cycle Together with IORQ indicates an Int Ack cycle RFSH Refresh (output, active Low). Together with MREQ indicates refresh cycle. Lower 7-bits address is refresh address to DRAM

Z80 Pin Description INT Interrupt Request (input, active Low). Interrupt Request is generated by I/O devices. Checked at the end of the current instruction If flip-flop (IFF) is enabled. NMI Non-Maskable Interrupt (Input, negative edge-triggered). Higher priority than INT. Recognized at the end of the current Instruction Independent of the status of IFF Forces the CPU to restart at location 0066H.

Z80 Pin Description BUSREQ Bus Request (input, active Low). higher priority than NMI recognized at the end of the current machine cycle. forces the CPU address bus, data bus, and MREQ, IORQ, RD, and WR to high-imp. BUSACK Bus Acknowledge (output, active,Low) indicates to the requesting device that address, data, and control signals MREQ, IORQ, RD, and WR have entered their high-impedance states.

Z80 Pin Description RESET Reset (input, active Low). RESET initializes the CPU as follows: Resets the IFF Clears the PC and registers I and R Sets the interrupt status to Mode 0. During reset time, the address and data bus go to a high-impedance state And all control output signals go to the inactive state. must be active for a minimum of three full clock cycles before the reset operation is complete.

Z80 CPU

Z80 Programming Model

Register Set A : Accumulator Register F : Flag register Two sets of six general-purpose registers may be used individually as 8-bit A F B C D E H L (A’ F’ B’ C’ D’ E’ H’ L’) or in pairs as 16-bit registers AF BC DE HL (AF’ BC’ DE’ HL’) The Alternative registers (A’ F’ B’ C’ D’ E’ H’ L’) not visible to the programmer but can access via: EXX (BC)<->(BC') , (DE)<->(DE') , (HL)<->(HL') EX AF, AF ’ (AF)<->(AF') what is this instruction useful for?

Register Set(cont) 4 16-bit registers hold memory address (pointers) index registers (IX) and (IY) are 16-bit memory pointers 16 bit stack pointer (SP) Program counter (PC) PC points to the next opcode to be fetched from ROM when the µP places an address on the address bus to fetch the byte from memory, it then increments the program counter by one to the next location Special purpose registers I : Interrupt vector register. R : memory Refresh register

Flag Register S Sign Flag (1:negativ)* Z Zero Flag (1:Zero) H Half Carry Flag (1: Carry from Bit 3 to Bit 4)** P Parity Flag (1: Even) V Overflow Flag (1:Overflow)* N Operation Flag (1:previous Operation wassubtraction)** C Carry Flag (1: Carry from Bit n-1 to Bit n, with n length of operand) *: 2-complement number representation **: used in DAA-operation for BCD-arithmetic

DAA - Decimal Adjust Accumulator Adjusts the content of the Accumulator A for BCD addition and subtraction operations such as ADD, ADC, SUB, SBC, and NEG according to the table: before DAA after DAA Op N C Bits 4-7 H Bits 0-3 A=A+.. ADD ADC 0-9 00 0-8 A-F 06 1 0-3 60 9-F 66 0-2 SUB SBC NEG 6-F FA 7-F A0 9A

Instruction cycles, machine cycles and “T-states” Instruction cycle is the time taken to complete the execution of an instruction Machine cycle is defined as the time required to complete one operation of accessing memory, accessing IO, etc. T-state = 1/f (f:Z80 Clock Frequency) f= 4MHZ  T-state=0.25 uS

Basic CPU Timing Example

Opcode Fetch Bus Timings (M1 Cycle)

The R register Is increased at every first machine cycle (M1). Bit 7 of it is never changed by this; only the lower 7 bits are included in the addition. So bit 7 stays the same Bit 7 can be changed using the LD R,A instruction. LD A,R and LD R,A access the R register after it is increased R is often used in programs for a random value, which is good but of course not truly random. the block instructions decrease the PC with two, so the instructions are re-executed.

Memory read/write cycle

Adding One Wait State to an M1 Cycle

Adding One Wait State to Any Memory Cycle

IO read/write cycle During I/O operations a single wait state is automatically inserted

Bus Request/Acknowledge Cycle

Interrupt Request/Acknowledge Cycle Two wait states are automatically added to this cycle

Non-Maskable Interrupt Request Operation

M1 Refresh Cycle Takes 4T to 6Ts Z80 includes built in circuitry for refreshing DRAM This simplifies the external interfacing hardware DRAM consists of MOS transistors, which store Information as capacitive charges; each cell needs to be periodically refreshed During T3 and T4 (when Z80 is performing internal ops), the low order address is used to supply a 7-bit address for refresh

Wait Signal the Z80 samples the wait signal during T2 if low then Z80 adds wait states to extend the machine cycle used to interface memories with slow response time Slow memory is low cost

Interrupts There are two types of interrupts: non mask-able (NMI) Could not be masked Jump to 0066H of memory mask-able(INT) Has 3 mode Can be set with the IM x Instruction IM 0 sets Interrupt mode 0 IM 1 sets Interrupt mode 1 IM 2 sets Interrupt mode 2

Interrupt Modes Mode 0: Mode 1: Mode 2: An 8 bit opcode is Fetched from Data BUS and executed The source interrupt device must put 8 bit opcode at data bus 8 bit opcode usually is RST p instructions Mode 1: A jump is made to address 0038h No value is required at data bus Mode 2: A jump is made to address (register I × 256 + value from interrupting device that puts at bus) I is high 8 bit of interrupt vector Value is low 8 bit of interrupt vector

Z80 CPU Instruction Description 158 different instruction types Including all 78 of the 8080A CPU. Instruction groups Load and Exchange Block Transfer and Search Arithmetic and Logical Rotate and Shift Bit Manipulation (Set, Reset, Test) Jump, Call, and Return Input/Output Basic CPU Control

Addressing Modes Immediate Immediate Extended Modified Page Zero Addressing (rst p) Relative Addressing Jump Relative (2 byte) One Byte Op Code 8-Bit Two’s Complement Displacement (A+2) Extended Addressing Absolute jump One byte opcode 2 byte address Indexed Addressing (Index Register + Displacement) (IX+d) 2 byte opcode 1 byte displacement

Addressing Modes(cont.) Register Addressing LD C,B Implied Addressing Op Code implies other operand(s) ADD E Register Indirect Addressing 16-bit CPU register pair as pointer (such as HL) ADD (HL) Bit Addressing set, reset, and test instructions. SET 3,A RES 7,B

Minimal Configuration of a Z80 Microcomputer

Z80 Memory connection CPU 16 bit address bus  64 k memory(max) CPU 8 bit data bus  8 bit data width Generally should be connected Data to data Address to address Wr to wr Rd to rd Mreq to cs

Memory connection (cont.) If only one RAM chip Full size (64 kb capacity) RAM 64 kb Z80 CPU D7~D0 A15~A0

Memory connection (cont.) If RAM capacity was 32 kb A15 composed with MREQ RAM area is from 0000h to 7FFFh RAM 32 kb Z80 CPU D7~D0 A14~A0 A15

Memory connection (cont.) There is two 32 kb RAM Problem: Bus Conflict. The two memory chips will provide data at the same time when microprocessor performs a memory read. Solution: Use address line A15 as an “arbiter”. If A15 outputs a logic “1” the upper memory is enabled (and the lower memory is disabled) and vice-versa.

Memory connection (cont.) There is two 32 kb RAM A15 applied to select one RAM chip Two RAM area is from 0000h to 7FFFh (RAM1) and 8000h to FFFFh (RAM1) RAM 32 kb Z80 CPU D7~D0 A14~A0 A15

Memory connection (cont.) 32 kb ROM and 32 kb RAM ROM doesn’t have wr signal ROM 32 kb Z80 CPU D7~D0 A14~A0 RAM A15

Memory connection (cont.) There is 4 memory chip A14 and A15 applied to chip selection ROM 16 kb D7~D0 A13~A0 RAM A15 A14 En S0 S1 Z80 CPU

Address Bit Map Selects chip Selects location within chips A15 to A0 (HEX) AA AA 11 11 54 32 AAAA 1198 10 7654 3210 Memory Chip 0000h 3FFFh 00 00 00 11 0000 1111 ROM 4000h 7FFFh 01 00 01 11 RAM1 8000h BFFFh 10 00 10 11 RAM2 C000h FFFFh 11 00 RAM3

Memory Map ROM Represents the memory type RAM1 Address area of each memory chip Empty area 0000h 3FFFh ROM 16k 4000h 7FFFh RAM1 8000h BFFFh RAM2 C000h FFFFh RAM3 ROM 16 kb D7~D0 A13~A0 RAM A15 A14 En S0 S1

Memory Map ROM RAM2 RAM3 0000h 3FFFh 4000h Empty Area cann’t write and read Read op. returns FFh value (usualy) Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM2 C000h FFFFh RAM3 ROM 16 kb D7~D0 A13~A0 A15 RAM A14 En S0 S1

Memory Map ROM RAM 0000h 3FFFh 4000h Empty Area cann’t write and read Read op. returns FFh value (usualy) Write op. cann’t store any value on it 0000h 3FFFh ROM 4000h 7FFFh Empty 8000h BFFFh RAM C000h FFFFh ROM 16 kb D7~D0 A13~A0 A15 RAM A14 En S0 S1

Full and Partial Decoding Full (exhaust) Decoding All of the address lines are connected to any memory/device to perform selection Absolute address : any memory location has one address Partial Decoding When some of the address lines are connected the memory/device to perform selection Using this type of decoding results into roll-over addresses (fold back or shading). roll-over address : any memory location has more than one address

Partial Decoding A15~A12 has no connection Then doesn’t play any role in addressing What is the Memory and Address Bit map? RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12

Partial Decoding Roll-over Address 0000h 0FFFh RAM 1000h 1FFFh RAM’ 2000h 2FFFh 3000h 3FFFh F000h FFFFh Every memory location has more than one address For example first RAM location has addresses: 0000h 1000h 2000h 3000h ……………. F000h Roll-over Address RAM 4 kb Z80 CPU D7~D0 A11~A0 X A15~A12 A15 to A0 (HEX) AAAA 1111 5432 1198 10 7654 3210 Memory Chip X000h XFFFh xxxx 0000 RAM

Partial Decoding X Z80 CPU A12 only connected to RAM A13 has no connection What is the memory map? D7~D0 D7~D0 D7~D0 ROM 4 kb RAM 8 kb A12~A0 A11~A0 A12~A0 A13 X Z80 CPU A14 A15

Partial Decoding 8 roll-over address for ROM 4 roll-over address for RAM ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 ROM X0x0 X0x1 RAM

Partial Decoding Conflict X RAM’ ROM ROM’ RAM Z80 CPU AAAA 1111 5432 0000h 1FFFh RAM’ 0FFFh ROM 1000h ROM’ 2000h 3FFFh 2FFFh 3000h 4000h 5FFFh 4FFFh 5000h 6000h 7FFFh 6FFFh 7000h 8000h 9FFFh RAM F000h FFFFh A000h BFFFh C000h DFFFh E000h Conflict ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 4k ROM X0x0 X0x1 8k RAM

Partial Decoding Conflict X ROM ROM’ RAM’ RAM Z80 CPU AAAA 1111 5432 0000h 1FFFh 0FFFh ROM 1000h ROM’ 2000h 3FFFh 2FFFh 3000h 4000h 5FFFh RAM’ 4FFFh 5000h 6000h 7FFFh 6FFFh 7000h 8000h 9FFFh F000h FFFFh A000h BFFFh C000h DFFFh RAM E000h ROM 4 kb Z80 CPU D7~D0 A11~A0 A12~A0 RAM 8 kb A14 A15 X A13 Conflict AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0xxx 0000 4k ROM X1x0 X1x1 8k RAM

Full (exhaustive) decoding AAAA 1111 5432 1198 10 7654 3210 Memory Chip 0000 0001 ROM 0010 0111 RAM A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A13 0000h-07FFh A12 0800h-0FFFh A11 7421 1000h-17FFh A10~A0 A10~A0 1800h-1FFFh D7~D0 2000h-27FFh 6116 RWM 2k8 A15 A14

Partial decoding 74138 A12~A0 A12~A0 D7~D0 D7~D0 Y0 Y1 Y2 Y3 Y6 Y4 Y7 1111 5432 1198 10 7654 3210 Memory Chip 0000 0001 ROM 001x x000 x111 RAM A12~A0 A12~A0 D7~D0 2764 EPROM 8k8 D7~D0 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A15 0000h-1FFFh A14 2000h-3FFFh A13 A10~A0 A10~A0 D7~D0 6116 RWM 2k8 GND VCC

1 Bit Memory With Separated I/O D7-D0 D7 D1 D0 Din Din Din A11~A0 Dout A11~A0 Dout A11~A0 Dout A11-A0 A11-A0 A11-A0 2147 RWM 4k1 2147 RWM 4k1 2147 RWM 4k1

What is the memory(addr. bit) map A12~A0 D7~D0 2764 EPROM 8k8 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 A15 0000h-1FFFh A14 2000h-3FFFh D7-D0 D7 D1 D0 A13 Din Din Din A11~A0 Dout A11~A0 Dout A11~A0 Dout A11-A0 A11-A0 A11-A0 2147 RWM 4k1 2147 RWM 4k1 2147 RWM 4k1 GND VCC

Adding RAM & ROM

Minimum Z80 Computer System

Z80-µP-Family (Typical Environment)

Z80 Input Output Z80 at most could have 256 input port and 256 output 8 bit port address is placed on A7–A0 pin to select the I/O device OUT (n), A n is 8 bit port address Content of A is data OUT (C), r Content of C is a port address r is a data register IN A, (n) Data is transfered to A IN r (C) Content of Reg C is a port address Input data is transfered to r (data reg)

Remember IO read/write cycle

Z80 and simple output port OUT (03), A Z80 CPU A14 A0 : D7 D6 WR IORQ A15 D5 D4 D3 D2 D1 D0 A 7 6 5 4 3 2 1 IOWR 74LS373 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 OE LE

Z80 and simple input port IN A, (02) Z80 CPU 74LS244 A15 A14 : A0 D7 5V A14 : A0 D7 Y0 A0 D6 Y1 A1 D5 Y2 A2 Z80 CPU D4 Y3 A3 D3 Y4 74LS244 A4 D2 Y5 A5 D1 Y6 A6 D0 Y7 A7 G1 G2 IORQ RD A A A A A A A A IORD 7 6 5 4 3 2 1

8088 and simple output port 8088 Minimum Mode 74LS373 A19 A18 : A0 D7 Q0 D6 D1 Q1 D5 D2 Q2 D4 D3 Q3 D3 D4 74LS373 Q4 D2 D5 Q5 8088 D1 D6 Q6 Minimum D0 D7 Q7 Mode LE OE IOR IOW A A A A A A A A A A A A A A A A IOW 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 5 4 3 2 1

8088 and simple input port What is this? 8088 Minimum Mode 74LS244 A19 5V A18 : What is this? A0 D7 Y0 A0 D6 Y1 A1 D5 Y2 A2 D4 Y3 A3 D3 Y4 74LS244 A4 D2 Y5 A5 8088 D1 Y6 A6 Minimum D0 Y7 A7 Mode G1 G2 IOR IOW A A A A A A A A A A A A A A A A IOW 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 5 4 3 2 1

Simplified Drawing of 8088 Minimum Mode A7 - A0 B7 - B0 DEN E 74LS245 DT / R DIR A7-A0 AD7 - AD0 D7 - D0 Q7 - Q0 GND OE 74LS373 LE A15-A8 A15 - A8 D7 - D0 Q7 - Q0 8088 GND OE 74LS373 LE A19-A16 A19/S6 - A16/ D7 - D4 Q7 - Q4 S3 D3 - D0 Q3 - Q0 GND OE 74LS373 ALE LE RD MEMR IO / M MEMW WR IOR IOW

Minimum Mode 220 bytes or 1MB memory Simplified Drawing of 1 MB A19 - A0 RD WR Simplified Drawing of 8088 Minimum Mode MEMR MEMW CS

What are the memory locations of a 1MB (220 bytes) Memory? A19 to A0 (HEX) AAAA 1111 9876 5432 1198 10 7654 3210 00000 0000 FFFFF Example: 34FD0 0011 0100 11111 1101 0000

Minimum Mode 512 kB memory What do we do with A19? Don’t connect it D7 - D0 D7 - D0 What do we do with A19? Don’t connect it Connect to cs What is the difference? A19 A18 - A0 A18 - A0 Simplified Drawing of 512 kB Memory 8088 Minimum Mode MEMR RD MEMW WR CS

512 kB Memory Map Don’t connect it Connect to cs A19 is not connected to the memory so even if the 8088 microprocessor outputs a logic “1”,the memory cannot “see” it. A19=0 is the same as A19=1 for Memory Connect to cs If A19=0 Memory chip act normal fanction 00000h 7FFFFh 512k Mem 80000h FFFFFh Mem’ 00000h 7FFFFh 512k Mem 80000h FFFFFh Empty

2  512 kB memory 512 kB RAM1 Simplified RAM2 Drawing of 8088 Minimum D7 - D0 A18 - A0 RD WR Simplified Drawing of 8088 Minimum Mode MEMR MEMW CS A19 RAM2

2  512 kB memory What are the memory locations of two consecutive 512KB (219 bytes) Memory? 00000h 7FFFFh 512k RAM1 80000h FFFFFh RAM2 AAAA 1111 9876 5432 1198 10 7654 3210 Memory Chip 0000 0111 ROM 1000 RAM

Interfacing four 256K Memory Chips to the 8088 Microprocessor : A0 D7 256KB : #4 D0 RD WR A19 CS A18 A17 A17 : : A0 A0 D7 D7 256KB : : #3 D0 D0 MEMR RD MEMW WR 8088 CS Minimum Mode A17 : A0 D7 256KB : #2 D0 RD WR CS A17 : A0 D7 256KB : #1 D0 RD WR CS

Interfacing four 256K Memory Chips to the 8088 Microprocessor Minimum Mode A17 A0 : D7 D0 MEMR MEMW A18 256KB #3 RD WR CS A19 #2 #1 #4 Interfacing four 256K Memory Chips to the 8088 Microprocessor

Memory chip#__ is mapped to: AAAA 1111 9876 5432 1198 10 7654 3210 Memory Chip RAM#1 RAM#2 RAM#3 RAM#4

Interfacing several 8K Memory Chips to the 8088 P Minimum Mode A12 A0 : D7 D0 MEMR MEMW A13 A14 8KB #2 RD WR CS #1 #? A15 A16 A17 A18 A19

Interfacing 128 8K Memory Chips to the 8088 P Minimum Mode A12 A0 : D7 D0 MEMR MEMW A13 A14 8KB #2 RD WR CS #1 #128 A15 A16 A17 A18 A19

Interfacing 128 8K Memory Chips to the 8088 P Minimum Mode A12 A0 : D7 D0 MEMR MEMW A13 A14 8KB #2 RD WR CS #1 #128 A15 A16 A17 A18 A19 Interfacing 128 8K Memory Chips to the 8088 P

Memory chip#__ is mapped to: AAAA 1111 9876 5432 1198 10 7654 3210 Memory Chip RAM#1 RAM#2 RAM#126 RAM#127 RAM#128

What is the Memory and Address Bit map? 74138 Y0 Y1 Y2 Y3 Y6 Y4 Y7 Y5 C B A G2A G2B G1 2764 EPROM 8k8 D7~D0 A12~A0 6116 RWM 2k8 A10~A0 A14 A13 A12 A15 7408 VCC 74244 input