Design KIT: Critical Conduction Mode (CRM) PFC Circuit All Rights Reserved Copyright (C) Bee Technologies Corporation 20101

Contents Introduction Application Circuit Design Specification Time Scaling Application Circuit with Time Scaling ( tscale =10 ) Common Mode Choke Coil for PFC Design Steps (1-8) Switching Devices V PEAK and I PEAK at Steady State Switching Devices V PEAK and I PEAK at Start Up Appendix A.Excel Calculation Sheet B.Simulation Index All Rights Reserved Copyright (C) Bee Technologies Corporation 20122

Introduction Most electronic ballasts and switching power supplies use a bridge rectifier and a bulk storage capacitor to derive raw dc voltage from the utility ac line, figure above: V in =100V ac, 50Hz and P O =200W. All Rights Reserved Copyright (C) Bee Technologies Corporation I line V bulk

Introduction The Uncorrected Power Factor rectifying circuit draws current from the ac line when the ac voltage exceeds the capacitor voltage (V bulk ). The current (I line ) is non- sinusoidal. This results in a poor power factor condition where the apparent input power is much higher than the real power, figure above, power factor ratios of 0.5 to 0.7 are common. All Rights Reserved Copyright (C) Bee Technologies Corporation |V AC, in, 100V | ( V PEAK, in =100*  2=141.42V) and V bulk |I line | Power Factor Ratio = P in, avg. /( V in, rms * I in, rms )

Introduction The Power Factor Correction (PFC) circuit, as an off-line active preconverter, is designed to draw a sinusoidal current from the AC line that is in phase with input voltage. As a result, the power factor ratio is improved to be near to ideal (1). The TB6819AFG is a critical conduction mode (CRM) PFC controller IC. The description including equation and constants as a guide to understand its designing process is included in this document. All Rights Reserved Copyright (C) Bee Technologies Corporation I line V DC, OUT

Introduction The poor power factor load is corrected by keeping the ac line current sinusoidal and in phase with the line voltage. This results with power factor ratio is All Rights Reserved Copyright (C) Bee Technologies Corporation V AC, in, 100V and V DC, OUT, 400V I line Power Factor Ratio = 0.85 *simulation result at tscale = 10

Application Circuit All Rights Reserved Copyright (C) Bee Technologies Corporation V AC, in =85-265V AC P O = 200W, V DC, OUT = 400V DC *Analysis directives:.TRAN 0 20ms 0 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Application Circuit All Rights Reserved Copyright (C) Bee Technologies Corporation V AC, in, 100V and V DC, OUT, 400V I line Power Factor Ratio = 0.85 Total simulation time = seconds

Design Specification This application circuit is for 400V DC /200W output Critical Conduction Mode (CRM) PFC Circuit : V AC, in,min = 85 (V AC ) V AC, in,max = 265 (V AC ) V O = 400 (V DC ) P o = 200 (W) fs = 20kHz ~ 150kHz, 50kHz  (assumed) = 90% Control IC : Part # TTB6819AFG (PFC Controller IC) Switching Technique: Critical Conduction Mode (CRM) All Rights Reserved Copyright (C) Bee Technologies Corporation 20129

Time Scaling The transient (cycle-by-cycle) simulation of PFC circuits is really time (and memory) consuming exercise, even with a fast computer. There is a way to speed up simulations by artificially altering some of the key element values by using of time scaling ratio (tscale), passed as a parameter to the simulation engine: F line = F line  tscale C 2 = C 2  tscale C 3 = C 3  tscale C 4 = C 4  tscale C 5 = C 5  tscale All Rights Reserved Copyright (C) Bee Technologies Corporation

Application Circuit with Time Scaling ( tscale =10 ) All Rights Reserved Copyright (C) Bee Technologies Corporation V AC, in =85-265V AC P O = 200W, V DC, OUT = 400V DC *Analysis directives:.TRAN 0 2ms 0 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Application Circuit with Time Scaling ( tscale =10 ) All Rights Reserved Copyright (C) Bee Technologies Corporation V AC, in, 100V and V DC, OUT, 400V I line Power Factor Ratio = 0.85 Total simulation time = seconds

Common Mode Choke Coil for PFC To model a simple common mode choke coil, the SPICE primitive k, which describes the coupling ratio between L1 and L2, can be used. COUPLING=1 of K_Linear means there is no leakage inductance in the common mode choke coil model. N is a ratio of L2 turns and L1 turns, or N2/N1 Input the parameters: L as an L1 inductance value and N, then L2 is calculated using equation: L2 = N 2  L1 All Rights Reserved Copyright (C) Bee Technologies Corporation

Design Steps (1-8) (1)Output Voltage and Feedback Circuit (2)Output Capacitor (3)L1 Inductance (4)Input Capacitor (5)Auxiliary Winding L2 (6)Multiplier Input Circuit (MULT) (7)Current Detection Circuit (IS) (8)Zero Current Detection Circuit (ZCD) All Rights Reserved Copyright (C) Bee Technologies Corporation

(1) Output Voltage and Feedback Circuit The output voltage is resistively divided and applied to the error amplifier, to set the V O the R1 and R2 resistor value should satisfy the following equation : *With V O =400V and R2=1.5M , R1 is calculated to be 9.47k , however a resistor of 9.53k , which is available in the E96 series, is used as R1 (actual). All Rights Reserved Copyright (C) Bee Technologies Corporation Output DC Voltage,VOVO 400V Error Amplifier Reference VoltageV err 2.51V R21.5 MM R19.47 kk R1 (actual) 9.53* kk

(2) Output Capacitor The output capacitance C2 is determined so that the PFC output ripple voltage dose not exceed the V OPV-2, for the capacitor selection, the following equation should be satisfied : The value of V OVP-2, min and Verr, min are inform in the TB6819AFG datasheet. All Rights Reserved Copyright (C) Bee Technologies Corporation POPO 200W f in 50Hz VOVO 400V V OVP-2, min 2.63V V err, min 2.46V C2  41 FF C2 used 200 FF

Simulation of Step (1) and (2) All Rights Reserved Copyright (C) Bee Technologies Corporation V in = 100Vac with frequency 50Hz, tscale = 10 R1=9.53k  and R2=1.5M  I load = 0.5A as P O =200W at V O =400V C2 = 200  F *Analysis directives:.TRAN 0 4ms 0 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Simulation of Step (1) and (2) All Rights Reserved Copyright (C) Bee Technologies Corporation V AC, in, =100V ( V PEAK, in, =100*1.4142=141.4V) V(FB IN), V OVP-2, min. (2.63V), and Verr,min(2.46V) V O =400Vdc with 2  f line ripple Total simulation time = seconds

(3) L1 Inductance The switching frequency  fs (Hz) depends on the L1 inductance and input/output condition which the equation and the calculation data are as shown below. *The fs value should be within 20kHz and 150kHz, to avoid an occurrence of EMI problem, fs=50kHz is used. All Rights Reserved Copyright (C) Bee Technologies Corporation Output DC Voltage,VOVO 400V Minimum AC Input Voltage,V AC, in, min 85V Power Efficiency,  (assumed) 90% Switching Frequency,fs*50kHz Output Power,POPO 200W Calculated Inductance,L1 (calculated) 227 HH Selected (Actual) Inductance,L1 (actual) 230 HH

(4) Input Capacitor C1 should be capable of supplying energy stored in the L1 while the FET is on. Assumed that the on/off duty is 50%, the C1 should be temporarily able to supply twice the current. A current reaches its maximum at the V AC, in, min. Thus, the following relationship should be satisfied: All Rights Reserved Copyright (C) Bee Technologies Corporation L1230 HH POPO 200W V AC, in, min 85V C1  0.35 FF C1 used 1 FF

Simulation of Step (3) and (4) All Rights Reserved Copyright (C) Bee Technologies Corporation V in, min = 85Vac with frequency 50Hz, tscale = 10 I load = 0.5A as P O =200W at V O =400V The Calculated L1 value 227  H (adjusted 230  H is used) I(L1) C1 = 1  F *Analysis directives:.TRAN 0 20ms 16m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Simulation of Step (3) and (4) All Rights Reserved Copyright (C) Bee Technologies Corporation V O =400Vdc with high switching ripple I(L1) Switching Control Signal, fs = 48.4 kHz Total simulation time = seconds

(5) Auxiliary Winding L2 The auxiliary winding L2 is used to detect the zero inductor current condition of the inductor L1. Since the maximum reference voltage for the ZCD comparator is 1.9V (the IC specification), N1/N2 should meet the following condition: Where N1 is the number of winding of turns of L1, N2 is that of L2 *To ensure that the design requirements are met, N1/N2 should preferably about 10 (9.6 is used) to allow for design margins. All Rights Reserved Copyright (C) Bee Technologies Corporation Output DC Voltage,VOVO 400V Maximum AC Input Voltage,V AC, in, max 265V Calculated Turn Number Ratio,N1/N2< 14 Selected Transformer Turn Ratio,N1/N2 (actual) 9.6*

Simulation of Step (5) All Rights Reserved Copyright (C) Bee Technologies Corporation N1/N2=9.6, input parameter N = N2/N1 = 1/9.6 I(L1) V in, min = 265Vac with frequency 50Hz, tscale = 10 I load = 0.5A as P O =200W at V O =400V *Analysis directives:.TRAN 0 4ms 2ms 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Simulation of Step (5) All Rights Reserved Copyright (C) Bee Technologies Corporation V O =400V and P O =200W V AC, in, min =265V ( V PEAK, in, min =265*1.4142=374.8V) I(L1) V(ZCD) and the maximum reference voltage of the TB6819AFG’s ZCD comparator, 1.9V Total simulation time = seconds

(6) Multiplier Input Circuit (MULT) The AC input supply voltage (sine  wave) is applied to the multiplier by dividing a full-wave rectified voltage waveform. The IC startup threshold voltages of the Brown Out Protection (BOP) function = 0.75V and the MULT linear input voltage range of the multiplier = 0 to 3V, the R9 and R10 resistor should satisfy the following condition: with excel calculation sheet PFC_Cal-Sht.xlsx you can input R9 and R10 values, then check the calculated BOP and Linear MULT values to be within the maximum values. All Rights Reserved Copyright (C) Bee Technologies Corporation Maximum AC Input Voltage,V AC, in, min 400V Maximum AC Input Voltage,V AC, in, max 265V R9R9 3 MM R kk Minimum Condition forBOP0.875> 0.75 Maximum Condition forLinear MULT2.728< 3 and

Simulation of Step (6) at V in, max All Rights Reserved Copyright (C) Bee Technologies Corporation V in, max = 265Vac with frequency 50Hz, tscale = 10 I load = 0.5A as P O =200W at V O =400V R10=3M  and R11=22k  *Analysis directives:.TRAN 0 4ms 2ms 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Simulation of Step (6) at V in, max All Rights Reserved Copyright (C) Bee Technologies Corporation Full-wave rectified voltage V AC, in, max =265V ( V PEAK, in, min =265*1.4142=374.8V) V(MULT) < MULT linear input maximum voltage (3V) Total simulation time = seconds

Simulation of Step (6) at V in, min All Rights Reserved Copyright (C) Bee Technologies Corporation R10=3M  and R11=22k  V in, min = 85Vac with frequency 50Hz, tscale = 10 I load = 0.5A as P O =200W at V O =400V *Analysis directives:.TRAN 0 20ms 16m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Simulation of Step (6) at V in, min All Rights Reserved Copyright (C) Bee Technologies Corporation Full-wave rectified voltage V AC, in, min =85V ( V PEAK, in, min =85*1.4142=120.2V) V(MULT) > BOP threshold voltage (0.75V) Total simulation time = seconds

(7) Current Detection Circuit (IS) Iq1 (power switch current) is converted into voltage by R7, then applied to the IS pin. The R7 resistor value calculation follows these steps: 1)The maximum current of the Q1 current, Iq1 (max) should allow the output power P O to meet the specification. Therefore, the following equation should be satisfied: 2)the IS pin peak voltage (Visp) is calculated using the following equation: 3)R7 = Visp / Iq1(max.). All Rights Reserved Copyright (C) Bee Technologies Corporation Minimum ac input voltage,V AC, in, min 85V Output power,POPO 200W Power efficiency,  (assumed) 90% R93 MM R1022 kk Power switch current,Iq1(max.)5.23A TB6819AFG IS pin peak voltageVisp0.57V R70.11 

Simulation of Step (7) All Rights Reserved Copyright (C) Bee Technologies Corporation Iq1 R7 = 0.11  V in, min = 85Vac with frequency 50Hz, tscale = 10 I load = 0.5A as P O =200W at V O =400V R10=3M  and R11=22k  *Analysis directives:.TRAN 0 20ms 16m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Simulation of Step (7) All Rights Reserved Copyright (C) Bee Technologies Corporation Iq1 V(MULT) V(IS) Total simulation time = seconds

(8) Zero Current Detection Circuit (ZCD) The auxiliary winding L2 is connected to the ZCD pin. The current through L2 is limited to ZCD pin rated current (3mA) by using the current limiting resistor R6. The following relationship should be satisfied depending on whether the external FET is on or off: FET = On: FET = Off: A resistor of 68k  is used for limiting the current to 1/5 of the rated current All Rights Reserved Copyright (C) Bee Technologies Corporation V AC, in, max 265V N2/N11/9.6W VOVO 400V FET = ON, R6 >13.0 kk FET = OFF, R6 >13.9 kk R6 (actual) 68 kk

Simulation of Step (8) All Rights Reserved Copyright (C) Bee Technologies Corporation ON/OFF R6 = 68k  V in, max = 265Vac with frequency 50Hz, tscale = 10 I load = 0.5A as P O =200W at V O =400V R10=3M  and R11=22k  *Analysis directives:.TRAN 0 4ms 2ms 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Simulation of Step (8) All Rights Reserved Copyright (C) Bee Technologies Corporation V AC, in, max =265V V(VOUT) I(R6) and 1/5 of the ZCD rated current (3mA/5) Total simulation time = seconds

Switching Devices V PEAK and I PEAK at Steady State All Rights Reserved Copyright (C) Bee Technologies Corporation V in, min = 85Vac with frequency 50Hz, tscale = 10 I load = 0.5A as P O =200W at V O =400V I(D2) Switching Diode, D2 *Analysis directives:.TRAN 0 20ms 16m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u ID(Q1) Switching MOSFET, Q1

Switching Devices V PEAK and I PEAK at Steady State All Rights Reserved Copyright (C) Bee Technologies Corporation D2 V KA, Peak ≈ 400V at steady state Total simulation time = seconds D2 I F, Peak ≈ 12A at steady state Q1 V DS, Peak ≈ 400V at steady state Q1 I D, Peak ≈ 7.2A at steady state

Switching Devices V PEAK and I PEAK at Start Up All Rights Reserved Copyright (C) Bee Technologies Corporation V in, min = 85Vac with frequency 50Hz, tscale = 40 I load = 0.5A as P O =200W at V O =400V I(D2) Switching Diode, D2 *Analysis directives:.TRAN 0 10ms 0m 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 40.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u ID(Q1) Switching MOSFET, Q1 Rectifier Diode, DB1-4

Switching Devices V PEAK and I PEAK at Start Up All Rights Reserved Copyright (C) Bee Technologies Corporation V(VOUT) at start up Total simulation time = seconds D2 V KA, Peak ≈ 400V and I F, Peak ≈ 16A at start up Q1 V DS, Peak ≈ 400V and I D, Peak ≈ 10A at start up DB1-4 I F, Peak ≈ 10A at start up

Simulation with Models from the SpicePark (1/4) All Rights Reserved Copyright (C) Bee Technologies Corporation Capacitor model MOSFET professional model Schottky diode model Replace some default model with models from SpicePark *Analysis directives:.TRAN 0 2ms 0 100n.OPTIONS ABSTOL= 100n.OPTIONS GMIN= 1.0E-8.OPTIONS ITL1= 500.OPTIONS ITL2= 200.OPTIONS ITL4= 100.OPTIONS RELTOL= 0.01.OPTIONS VNTOL= 100u

Simulation with Models from the SpicePark (2/4) All Rights Reserved Copyright (C) Bee Technologies Corporation V(VOUT) with high frequency ripple which is caused by ESR and ESL of the capacitor model. Gate charge characteristics is include in the MOSFET Professional model. V(V1) I (L1) V(V2) Total simulation time = seconds

Simulation with Models from the SpicePark (3/4) All Rights Reserved Copyright (C) Bee Technologies Corporation The Simulation Waveform with the defaults models V(V1) I (L1) V(V2) V(VOUT) without high frequency ripple which is caused by ESR and ESL of the capacitor model. Gate charge characteristics is not include in the default model. Total simulation time = seconds

Simulation with Models from the SpicePark (1/4) All Rights Reserved Copyright (C) Bee Technologies Corporation SpicePark of MOSFET model Select the device which is capable of handling the simulated peak values.

Excel Calculation Sheet (1/2) All Rights Reserved Copyright (C) Bee Technologies Corporation Design Specification V AC, in,min 85V V AC, in,max 265V f in 50Hz VOVO 400V POPO 200W fs50kHz  (assumed) 90% (1) Output Voltage & Feedback Circuit R2R2 1.5 MM ; Input R2 value, the R1 for the VO specification is auto-calculated R1R kk R 1 (actual) 9.53 kk (2) Output Capacitor V OVP-2, MIN. 2.63V ; V OVP-2, MIN. and V err, MIN. are TB6819AFG electrical characteristics V err, MIN. 2.46V C2 ³41uFuF (3) L1 Inductance L1227mH L1 (actual) 230mH

Excel Calculation Sheet (2/2) All Rights Reserved Copyright (C) Bee Technologies Corporation (4) Input Capacitor C1 ³0.35 FF C1 (actual) 1 FF (5) Auxiliary Winding L2 N1/N2 <14 N1/N2 (actual) 9.6 (6) Multiplier Input Circuit (MULT) R9R9 3 MM ; Input R9 and R10 values, then check the BOP and the Linear MULT values R kk Codition: BOP0.875> 0.75 Linear MULT2.728< 3 (7) Current Detection Circuit (IS) Iq1(max.)5.23A Visp0.57V R7R  (8) Zero Current Detection Circuit (ZCD) FET=ON, R8 >13.0 kk FET=OFF, R8 >13.9 kk R 8 (actual) 68 kk ; limiting the current to 1/5 of the rated current. Remark Input your design specification and your selected parameters. The numbers in the green font are auto- calculated numbers. The numbers in the blue font are the design actual selected (used) number.

Simulation Index All Rights Reserved Copyright (C) Bee Technologies Corporation SimulationsFolder name 1.Application Circuit Application Circuit with Time Scaling ( tscale =10 ) Simulation of Step (1) and (2) Simulation of Step (3) and (4) Simulation of Step (5) Simulation of Step (6) at V in, max Simulation of Step (6) at V in, min Simulation of Step (7) Simulation of Step (8) Switching Devices V PEAK and I PEAK at Steady State Switching Devices V PEAK and I PEAK at Start Up APPCKT APPCKT_tscale STEP1-2 STEP3-4 STEP5 STEP6_INMAX STEP6_INMIN STEP7 STEP8 IVPEAK-SS IVPEAK-SU Libraries : 1...\part\tb6819afg\tb6819afg.lib 2...\part\parts.lib