Unit 12 Registers and Counters Ku-Yaw Chang Assistant Professor, Department of Computer Science and Information Engineering Da-Yeh University

22004/05/06Registers and Counters Outline 12.1Registers and Register Transfers 12.2Shift Registers 12.3Design of Binary Counters 12.4Counters for Other Sequences 12.5Counter Design Using S-R and J-K Flip-Flops Flip-Flops 12.6Derivation of Flip-Flop Input Equations -- Summary -- Summary

32004/05/06Registers and Counters Registers Several D flip-flops may be grouped together with a common clock. Each flip-flop can store one bit of information. The following register store four bits of information The following register store four bits of information

42004/05/06Registers and Counters Registers Asynchronous clear inputs A common clear signal – ClrN, requiring a logic 0 to clear flip- flops A common clear signal – ClrN, requiring a logic 0 to clear flip- flops Gating the clock can cause timing problems

52004/05/06Registers and Counters Registers Flip-flops with clock enable are available Load = 0 : the clock is disabled, and the register holds its data Load = 0 : the clock is disabled, and the register holds its data Load = 1 : the clock is enabled, and the data applied to the D inputs will be loaded into the flip-flops (after the falling edge) Load = 1 : the clock is enabled, and the data applied to the D inputs will be loaded into the flip-flops (after the falling edge)

62004/05/06Registers and Counters Registers 4-bit register using bus notation

72004/05/06Registers and Counters Data Transfer Between Registers

82004/05/06Registers and Counters Logic Diagram for 8-Bit Register

92004/05/06Registers and Counters Data Transfer Using a Tri-State Bus

102004/05/06Registers and Counters Parallel Adder with Accumulator

112004/05/06Registers and Counters Adder Cell with Multiplexer