Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Basic fabrication steps. n Transistor structures. n Basic transistor behavior. n Latch up.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Fabrication services n Educational services: –U.S.: MOSIS –EC: EuroPractice –Taiwan: CIC –Japan: VDEC n Foundry = fabrication line for hire. n (A building equipped for the casting of metal or glass, microsoft office dictionary) –Foundries are major source of fab capacity today.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Wafers A wafer is a thin slice of semiconducting material, such as a silicon crystal, upon which microcircuits are constructed by doping (for example, diffusion or ion implantation, etching, and deposition of various materials. n Wafers are cut out of silicon boules n A boule is a single crystal silicone from which wafers are cut using diamond saws. n

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Fabrication Process n Once the wafers are prepared, many process steps are necessary to produce the desired semiconductor integrated circuit. In general, the steps can be grouped into four areas: n Front end processing (formation of transistors on silicon wafers) n Back end processing (interconnection of transistors by metal wires) n Test n Packaging n In semiconductor device fabrication, the various processing steps fall into four general categories: deposition, removal, patterning, and modification of electrical properties. n

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Deposition n Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies consist of physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. n

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Removal or Etching Process n Removal processes are any that remove material from the wafer either in bulk or selective form and consist primarily of etch processes, both wet etching and dry etching such as reactive ion etch (RIE). Chemical mechanical planarization (CMP) is also a removal process used between levels. n

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Masking and Patterning Patterning covers the series of processes that shape or alter the existing shape of the deposited materials and is generally referred to as lithography. For example, in conventional lithography, the wafer is coated with a chemical called a photoresist. The photoresist is exposed by a stepper, a machine that focuses, aligns, and moves the mask, exposing select portions of the wafer to short wavelength light. The unexposed regions are washed away by a developer solution. After etching or other processing, the remaining photoresist is removed by plasma ashing. n Many modern chips have eight or more levels produced in over 300 sequenced processing steps. n

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Fabrication processes n IC built on silicon substrate (mono crystal silicone): –some structures diffused into substrate; – other structures built on top of substrate. n Substrate regions are doped with n-type and p-type impurities. (n+,p+ = heavily doped) n When silicon is doped, n-type impurities (5-valence electron elements such as arsenic) charge silicon atoms with electrons, p-type impurities (3- valence electrons such as boron) charge them with holes n Wires made of polycrystalline silicon (poly), and/or multiple layers of aluminum (metal). n Silicon dioxide (SiO 2 ) is insulator. (is grown over Si by heating Si in a pure oxygen or water vapor atmosphere)

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Simple cross section substrate n+ p+ substrate metal1 poly SiO 2 (insulator) metal2 metal3 transistor via

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Photolithography Mask patterns are put on wafer using photo- sensitive material: A typical wafer is made out of extremely pure silicon that is grown into mono-crystalline cylindrical ingots (boules) up to 12 in (300 mm) in diameter using the Czochralski process. These ingots are then sliced into wafers about 0.75 mm thick and polished to obtain a very regular and flat surface.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Process steps First place tubs to provide properly-doped substrate for n-type, p-type transistors: (Front-end processing) p-tubn-tub substrate

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Process steps, cont’d. Pattern polysilicon before diffusion regions: p-tub poly gate oxide

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Process steps, cont’d Add diffusions, performing self-masking: p-tub poly n+ p+

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Process steps, cont’d Start adding metal layers: (Backend processing) p-tubn-tub poly n+ p+ metal 1 vias

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Transistor structure n-type transistor:

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR 0.25 micron transistor (Bell Labs) poly silicide source/drain gate oxide

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Transistor layout n-type (tubs may vary): w L

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Electrical Transistor Model n V gs : gate to source voltage n V ds : drain to source voltage n I ds : current flowing between drain and source n k’: transconductance > 0 n V t : threshold voltage > 0 for n-type <0 for p-type transistor. n W/L: width to length ratio

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Drain current characteristics

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Drain current n Linear region (V ds < V gs - V t ): –I d = k’ (W/L)[(V gs - V t )V ds V ds 2 ] –Not quite a linear relation between I d and V ds but the quadratic term becomes more negligible than the linear term as V ds approaches 0. This is typically the case with the absolute value of the threshold V t voltage remaining close to 0. n Saturation region (V ds >= V gs - V t ): –I d = 0.5k’ (W/L)(V gs - V t ) 2 –I d remains constant over changes in V ds –Increases with transconductance, channel width, and decreases with channel length.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR 0.5  m transconductances From a MOSIS process: n n-type: –k n ’ = 73  A/V 2 –V tn = 0.7 V n p-type: –k p ’ = 21  A/V 2 –V tp = -0.8 V

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Current through a transistor (At saturation) Example: Using 0.5  m transconductance parameter of 73  A/V 2, threshold voltage of 0.7 volts, and SCMOS rules ( main.html) with W 3, L = 2 : n Saturation current at V gs = 2V: I d = 0.5k’(W/L)(V gs -V t ) 2 = 93  A n Saturation current at V gs = 5V: I d = 1012  A ~ 1 mA

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Basic transistor parasitics n There are myriad parasitics and parasitics models. The ones considered here are the most widely-encountered parasitics. n Gate to substrate, also gate to source/drain. n Source/drain capacitance, resistance. CgCg substrate

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Basic transistor parasitics, cont’d n Gate capacitance C g. Determined by active area. n Source/drain overlap capacitances C gs, C gd. Determined by source/gate and drain/gate overlaps. Independent of transistor L. –C gs = C ol W (C ol is the unit overlap capacitance per  m 2, For small channel length, C ol might indirectly depend on L. ) –Gate/bulk overlap capacitance.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Latch-up n CMOS ICs have built-in undesirable parasitic silicon-controlled rectifiers (SCRs). n When powered up, SCRs can turn on, creating low-resistance path from power to ground. Current can destroy chip. n Early CMOS problem. Can be solved with proper circuit/layout structures.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Silicon Controlled Rectifier(SCR) Tyristor Circuit n In normal mode, no current flows over the pnpn path when the middle pn junction is reverse-biased. With the help of a gate pulse voltage, this pn junction can be forced into its breakdown region, making it conduct current. At that point, there will be a path of current from the anode to the cathode with no resistance even after the gate voltage is withdrawn. This is the basis for a high current from VDD to the ground (substrate) in MOS transistors, called the latch up. p p n n anode cathode gate FB RB

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Parasitic SCR circuitI-V behavior V Reverse voltage breakdown R s and R w control the bias voltage on the green diodes FB Breakdown FB

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Parasitic SCR structure n p p n n p Solution: connect the n-tub to the V DD When transistor on the right conducts, it turns on the transistor on the left, and this in turn forces the first transistor to draw more current, establishing a positive feedback loop.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Solution to latch-up Use tub ties to connect tub to power rail. Use enough to create low-voltage connection. Doping the tub at the point of contact reduces the resistance of contact, and this makes it more difficult for bipolar transistor to turn on.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Tub tie layout metal (V DD ) n-tub n+ You can learn more about latch up by downloading the article at