October 11, 20001

2 USB 2.0 Transceiver Macrocell Steve McGowan - Intel Corporation Clarence Lewis - Texas Instruments Haoran Duan - Agilent Technologies

October 11, USB 2.0 Transceiver Macrocell Interface Overview

October 11, Macrocell Requirements w Enable Peripherals w Does not address hubs and hosts – No downstream port support u Disconnect Detection u 40 bit EOP – No repeater support u Very implementation dependent u Requires separate port

October 11, Macrocell Requirements w Simplify the design process for peripheral vendors – Consolidate high speed logic in to a discrete module – Provide a “standard” USB 2.0 hardware interface w Minimize time to market – Isolate process dependent transceiver development u Enable standard library elements from ASIC vendors – Peripheral vendors can focus on product specific development u Easy port of existing USB 1.1 SIE logic Overview Enable High Volume Devices

October 11, USB Device Development w Assumptions – Prototyping u FPGA + UTMI Compliant Discrete Transceiver – Production u Low Volume Ô Gate Array + UTMI Compliant Discrete Transceiver u High Volume Ô ASIC + integrated UTMI Compliant Transceiver Macrocell Overview

October 11, Device Anatomy w USB Transceiver Macrocell (UTM) w Serial Interface Engine w Device Specific Logic Overview ASICASIC Serial Interface Engine Device Specific Logic Endpoint Logic …… SIE Control Logic SIE Control Logic USB 2.0 Endpoint Logic Device Hardware USB 2.0 Transceiver UTM Interface

October 11, Serial Interface Engine w SIE Control Logic – USB Transaction State Machine – PID, Address, and EP match logic – Checks receive completion status – Chains packets into transactions w Endpoint Logic – FIFOs and FIFO control Serial Interface Engine Endpoint Logic … SIE Control Logic Endpoint Logic Control Data In Data Out To Device Specific Logic To Transceiver Overview

October 11, Transceiver Macrocell w Converts USB signaling into a parallel interface – USB 2.0 compliant serial interface – Multiple Parallel Data Interface Options – Multiple Speed Options u HS/FS, FS Only, LS Only USB 2.0 USB 2.0 Transceiver Control Data In Data Out To SIE To Bus Overview

October 11, Macrocell Functions w HS and FS signaling and termination w HS receiver squelch w USB clock recovery w Bit stuffing w NRZI encoding w Serializing and deserializing w Data-rate tolerance w Data buffering w Single interface for HS/FS, FS or LS operation Overview

October 11, Block Diagram ControlControl ControlD-D+ DLLDLL FS Interface HS Interface Shared Logic ParallelInterfaceParallelInterface DLLDLL mux BitUnstufferBitUnstufferDeseralizerDeseralizer RX Holding Reg BitStufferBitStufferSeralizerSeralizer TX Holding Reg Reg To SIE Data To USB Overview

October 11, Macrocell Functions Interface Features w Packet Engine – Automatically handles SYNC Pattern and EOP w Flow Control – Compensates for Bit Stuffing and Data Rate Tolerance w Complete Primitives for Full Protocol Support w Speed Switching w Clock Generation w Power Control

October 11, Interface Options w Integrated Macrocell – 8-Bit Uni-directional – 16-Bit Uni-directional w Discrete Transceiver – 8-Bit Bi-directional – 16-Bit Bi-directional / 8-Bit Uni-directional Macrocell Functions

October 11, Bit Uni-Directional Interface Options DataIn(0-7)TXValidResetSusepsndMXcvrSelectTermSelectOpMode(0-1)DataOut(0-7)TXReadyRXActiveRXValidCLKRXErrorDPDMLineState(0-1) 8-Bit Interface

October 11, Bit Uni-Directional Interface Options DataIn(8-15) DataIn(0-7) TXValid TXValidH Reset SusepsndM XcvrSelect TermSelect OpMode(0-1)DataOut(8-15)DataOut(0-7)TXReadyRXActiveRXValidRXValidHCLKRXErrorDPDMLineState(0-1) 16-Bit Interface

October 11, Bit Bi-Directional w TXValid Determines data direction Interface Options DataOut(0-7)TXValidData(0-7)DataIn(0-7) 8-Bit Bi-Directional Interface

October 11, Bit Bi-Directional Interface Options DataBus16_8DataOut(8-15)DataOut(0-7)TXValidRXValidHData(8-15)Data(0-7)ValidHDataIn(8-15)DataIn(0-7)TXReadyTXValidH 16-Bit Bi-Directional Interface w ValidH provides multiplexed high-byte valid flag

October 11, Protocol Primitive Support w Resume Assertion w Resume Detection w Suspend Detection w Reset Detection w HS Detection Handshake Macrocell Functions

October 11, Clock Generation w Macrocell supplies clocks to the SIE w Frequency depends on implementation – HS/FS u 60 MHz 8-bit uni-directional u 30 MHz 16-bit uni- or bi-directional – FS Only u 48 MHz 8-bit uni-directional – LS Only u 6 MHz 8-bit uni-directional Macrocell Functions

October 11, Power Control w SuspendM signal – Shuts down clocks – Maintains terminations w Vendor determined Drive Current Control – Enabled during transmits – Enabled by receives – Always on DP DM HS_Current_Source_Enable HS_Drive_Enable HS_Data_Driver_Input High-speed Current Driver Macrocell Functions

October 11, USB 2.0 Transceiver Macrocell Interface Testing

October 11, Testing w UTMI Test Connector Specification w Test Environment - 3 board set – Off the shelf i960 eval board – Custom SIE card u FPGA, DPRAM, and Test Points – Daughter Card with UTMI Transceiver w Functionality – Packet Blaster u Single Packet operations – Device Emulator u Transaction level operations

October 11, UTMI Test Connector Specification w UTMI Test Connector – 100 Pins w Electrical interface – Timing – Levels w Mechanical design – PCB layout

October 11, Board Set w Processor Card – EVAL80960VH Evaluation Platform Board – RAM, ROM, FLASH, Serial Port w FPGA Card – Dual Port RAM - 64KB – FPGA - Quicklogic – Test Points w Transceiver Daughter Card – Discrete UTMI compliant transceiver – Custom circuitry Testing

October 11, Block Diagram USB 2.0 Transceiver Serial Interface Engine Transceiver / Macrocell i960i960 USB 2.0 DPRAMDPRAM I960 Local Bus UTM Interface UARTUARTFlashFlashDRAMDRAMRS-232RS-232 Device Specific Logic FPGAFPGA I960 Card FPGA Card Transceiver Daughter Card Testing

October 11, Mechanicals To USB Device Test Chip Daughter Card i960 Card FPGA Card PCI Slots (Power) RS-232 Connector CPUCPU FPGAFPGA DP RAM XcvrXcvr 100 Pin UTMI Connector RAMRAM Testing

October 11, Pinout Features w Vendor Status and Vendor Control support w Multiple Datapath Options Supported – 8-Bit Bi-Directional – 8-Bit Uni-Directional – 16-Bit Bi-Directional/8-Bit Uni-Directional w Vendor ID w 13 General Purpose I/O pins w Vbus Control

October 11, Pinout 1GPIO026GPIO151GND76GND 2GND27GND52System Clock77ValidH 3GPIO228VBUS_out53GND78DataBus16_8 4GND29GPIO354GND79VControl1 5GPIO430VendorID_055VControl080GND 6GPIO531Data1556GPIO681VDD 7GPIO732GND57VDD82Data14 8VDD33Data1358GPIO883Data12 9GND34Data1159VControl284GND 10VControl335GND60TxValid85Data10 11GPIO936Data961GPIO1086Data8 12GPIO1137Data762GND87VDD 13GND38VDD63GPIO1288Data6 14VControlLoadM39GND64IFType089 IFType1 15VStatus440Force_RxErr65GND90CLK 16VDD41Data566RxActive91Data4 17Reset42Data367OpMode092GND 18OpMode143GND68GND93Data2 19XcvrSelect44Data169VDD94Data0 20TermSelect45VStatus070VStatus195GND 21GND46GND71VStatus296VStatus3 22SuspendM47VBUS_in72RxValid97VStatus5 23LineState048VStatus673GND98VStatus7 24GND49VDD74RxError99VendorID_1 25LineState150Vdbus16_875TxReady100GND Testing

October 11, Next Steps w Get the USB 2.0 Transceiver Macrocell Interface (UTMI) Specification – – No Royalty w Design to the UTMI Specification w Get the UTMI Test Connector Specification – w Get your ASIC vendors to provide a UTMI Compliant Macrocells