Sayed Ahmed Computer Engineering, BUET, Bangladesh MSC, Computer Science, U of Manitoba, Canada Software Engineer/Developer, Canada Owner/President/Architect/Developer Justetc (Just et cetera) Technologies

 Still under construction  Will improve later  Motivation  Students taking Computer Engineering majors may not always know the names of the tools used in industries in Computer Hardware Engineering related jobs  Primarily tried to provide a list of the skills required  Learn them along with your study whether your university teaches them or not

 Bangladesh may not have many opportunities  Check Samsung R & D  Learn the tools well  Try companies in India, Taiwan, Singapore, and China  Then probably move to North America  Go back to Bangladesh and create a Hardware Industry  Or take MSc in related areas in North America or Australia  Apply to the related companies  Learn the tools mentioned and other related tools and languages very well

 Training and Education in Bangla:   SaLearningSchool.com SaLearningSchool.com  Training and Education in English:     Ask questions and get answers   Offline IT Training: 

 A list of the required/important courses can be found at    Related Courses   ons ons

 Some Tools you should know  Design & Simulation  Verilog  SystemVerilog  VHDL  SPECMAN  OVM/UVM/VMM environment  VCS  VERDI  DVE  CATS  JTV tools for Boundary Scan

 VLSI  SoC  ASIC  Computer Architecture

 Languages and Tools  C/C++/C#  Assembly Language  Linux/Unix  Scripting  Matlab

 From Wikipedia:   Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits.hardware description languagedigital circuitsregister-transfer levelabstractionanalog circuitsmixed-signal circuits  Tutorial 

 From Wikipedia   In the semiconductor and electronic design industry, SystemVerilog is a combined Hardware Description Language and Hardware Verification Language based on extensions to Verilog.semiconductorHardware Description LanguageHardware Verification LanguageVerilog

  VHDL (VHSIC Hardware Description Language) is a hardware description language used in electronic design automation to describe digital and mixed-signal systems such as field- programmable gate arrays and integrated circuits. VHDL can also be used as a general purpose parallel programming languageVHSIChardware description language electronic design automationdigitalmixed-signalfield- programmable gate arraysintegrated circuits 

 From Wikipedia   Specman is an EDA tool, that provides advanced automated Functional verification of hardware designs. It provides an environment for working with, compiling, and debugging testbench environments written in the e Hardware Verification Language. Specman also offers automated testbench generation to boost productivity in the context of block, chip, and system verification.EDAeHardware Verification Language  The Specman tool itself does not include an HDL-simulation environment (such as VHDL or Verilog.) To simulate an e-testbench with a design written in VHDL/Verilog, Specman must be run in conjunction with a separate HDL simulation tool. In principle, Specman can co-simulate with any HDL-simulator supporting standard PLI or VHPI interface, such as Cadence's NC-Sim or Verilog- XL, Synopsys's VCS, or Mentor's ModelSim, or Aldec's Riviera-PRO. But in practice, Specman is used almost exclusively with NC-Sim, where tighter product integration with NC-Sim offers both faster runtime performance and debug capabilities not available with other HDL-simulators.VHDLVerilogNC-SimVCSModelSimRiviera-PRONC-Sim

 Tutorial 

 The future  /2010/05/24/the-future-of-ovm-vmm-and-uvm.aspx /2010/05/24/the-future-of-ovm-vmm-and-uvm.aspx  OVM    OVM: first multi-vendor verification solution, so should be supported well in different simulator.  VMM: looks like faster than others especially for large chip when running in vcs.

  An end-of-test objection mechanism to ease the task of cleaning up at the end of a verification run  A callback mechanism that provides an alternative to the factory for customizing behavior  A report catcher to ease the task of customized report handling  A heartbeat mechanisms to monitor the liveness of verification components.

 An end-of-test objection mechanism to ease the task of cleaning up at the end of a verification run  A callback mechanism that provides an alternative to the factory for customizing behavior  A report catcher to ease the task of customized report handling  A heartbeat mechanisms to monitor the liveness of verification components.

 unctionalVerification/Pages/VCS.aspx unctionalVerification/Pages/VCS.aspx

 ebug/Pages/Verdi-ds.aspx ebug/Pages/Verdi-ds.aspx  Automated Debug System Overview The Verdi 3 ™ Automated Debug System is an advanced open platform for debugging digital designs with powerful technology that helps you comprehend complex and unfamiliar design behavior, automate difficult and tedious debug processes and unify diverse and complicated design environments.

 /04/cool-things-you-can-do-with-dve-part-1/ /04/cool-things-you-can-do-with-dve-part-1/  /04/cool-things-you-can-do-with-dve-part-2/ /04/cool-things-you-can-do-with-dve-part-2/  /04/cool-things-you-can-do-with-dve-part-3/ /04/cool-things-you-can-do-with-dve-part-3/

  AMD  AMD Selects NEW JTAG Tool to Raise the Bar on Quality Austin, Texas – March 24th, 2006 – SiliconAid Solutions, Inc. announced today that AMD (NYSE:AMD) has selected the SiliconAid’s JTV (JTAG verification) tool. The JTV tool provides a robust verification environment to ensure that your verilog design with JTAG and your BSDL (Boundary Scan Description Language) are fully consistent and comply with the IEEE and standards. "SiliconAid’s JTV JTAG tool has proven to be an extremely thorough and easy to use tool that provides excellent feedback. The transition was seamless and enabled us to continue important functionalities with virtually no interruption. As a result, we have a strong process driven by a great tool." - Tim Wood, AMD Fellow Complementary to an automated or custom JTAG design flow, JTV gives a quick, easy, and independent way to make sure your design is correct. JTV can output fault-simulated production test patterns and parametric tests. JTV is unique in its ability to verify that the chip design is JTAG- compliant and that the BSDL file accurately describes your JTAG design.

 scale_integration scale_integration  Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.integrated circuitstransistorssemiconductor communicationmicroprocessor

 Magic VLSI 

 VLSI  Verilog  SoC  ASIC  Computer Architecture  VHDL  Processors  Embedded Systems  IC  Perl

 C  EDA  Microprocessors  SystemVerilog  Logic Design  Hardware  Semiconductors  FPGA  Debugging  Cadence Virtuoso  Integrated Circuit...  Signal Integrity  ModelSim  Functional Verification  Manufacturing  Intel  ARM

 VLSI Chip design  Mixed Signal  TCL  Static Timing Analysis  Simulations  DFT  Circuit Design  Logic Synthesis  Digital Signal...  Microarchitecture  SPICE  Formal Verification  Analog  Assembly

 CMOS  Hardware Architecture  Physical Design  Low-power Design  RTL design  Timing Closure  PCIe  RTL coding  Primetime

 Ask Here