EECS Components and Design Techniques for Digital Systems FSMs 9/11/2007 Sarah Bird Electrical Engineering and Computer Sciences University of California, Berkeley Slides borrowed from David Culler Fa04 and Randy Katz Sp07

CS Fall 2007 – Moore and Mealy Machines - 2 Sequential Logic Implementation zModels for representing sequential circuits yFinite-state machines (Moore and Mealy) yRepresentation of memory (states) yChanges in state (transitions) zDesign procedure yState diagrams yState transition table yNext state functions

CS Fall 2007 – Moore and Mealy Machines - 3 Recall: What makes Digital Systems tick? Combinational Logic time clk

CS Fall 2007 – Moore and Mealy Machines - 4 Abstraction of State Elements zDivide circuit into combinational logic and state zLocalize feedback loops and make it easy to break cycles zImplementation of storage elements leads to various forms of sequential logic Combinational Logic Storage Elements Outputs State OutputsState Inputs Inputs

CS Fall 2007 – Moore and Mealy Machines - 5 Forms of Sequential Logic zAsynchronous sequential logic – state changes occur whenever state inputs change (elements may be simple wires or delay elements) zSynchronous sequential logic – state changes occur in lock step across all storage elements (using a periodic waveform - the clock) Clock

CS Fall 2007 – Moore and Mealy Machines - 6 In = 0 In = 1 In = 0In = Finite State Machine Representations zStates: determined by possible values in sequential storage elements zTransitions: change of state zClock: controls when state can change by controlling storage elements zSequential Logic ySequences through a series of states yBased on sequence of values on input signals yClock period defines elements of sequence

CS Fall 2007 – Moore and Mealy Machines - 7 Can Any Sequential System be Represented with a State Diagram? zShift Register yInput value shown on transition arcs yOutput values shown within state node DQDQDQ IN OUT1OUT2OUT3 CLK

CS Fall 2007 – Moore and Mealy Machines - 8 Two Kinds of FSMs zMoore Machine vs Mealy Machine Combinational Logic state state(t+1) = F ( state(t), input) Output (t) = G ( state(t), Input ) Input state state(t+1) = F ( state(t), input(t)) Output (t) = G ( state(t)) Input State / out Input State Input / Out

CS Fall 2007 – Moore and Mealy Machines bit up-counter Counters are Simple Finite State Machines zCounters yProceed thru well-defined state sequence in response to enable zMany types of counters: binary, BCD, Gray-code y3-bit up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000,... y3-bit down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111,...

CS Fall 2007 – Moore and Mealy Machines - 10 Verilog Upcounter module binary_cntr (q, clk) inputs clk; outputs [2:0] q; reg [2:0] q; reg [2:0] p; //Calculate next state case (q) 3’b000: p = 3’b001; 3’b001: p = 3’b010; … 3’b111: p = 3’b000; endcase clk) //next becomes current state q <= p; endmodule

CS Fall 2007 – Moore and Mealy Machines - 11 How Do We Turn a State Diagram into Logic? zCounter yThree flip-flops to hold state yLogic to compute next state yClock signal controls when flip-flop memory can change xWait long enough for combinational logic to compute new value xDon't wait too long as that is low performance

CS Fall 2007 – Moore and Mealy Machines - 12 FSM Design Procedure zStart with counters ySimple because output is just state ySimple because no choice of next state based on input zState diagram to state transition table yTabular form of state diagram yLike a truth-table zState encoding yDecide on representation of states yFor counters it is simple: just its value zImplementation yFlip-flop for each state bit yCombinational logic based on encoding

CS Fall 2007 – Moore and Mealy Machines bit up-counter current state next state FSM Design Procedure: State Diagram to Encoded State Transition Table zTabular form of state diagram zLike a truth-table (specify output for all input combinations) zEncoding of states: easy for counters – just use value

CS Fall 2007 – Moore and Mealy Machines - 14 C3C2C1N3N2N N1:= C1' N2:= C1C2' + C1'C2 := C1 xor C2 N3:= C1C2C3' + C1'C3 + C2'C3 := C1C2C3' + (C1' + C2')C3 := (C1C2) xor C3 notation to show function represent input to D-FF Implementation zD flip-flop for each state bit zCombinational logic based on encoding C1 C2 C3 N C1 C2 C3 N C1 C2 C3 N1

CS Fall 2007 – Moore and Mealy Machines - 15 Parity Checker FSM z“State Transition Diagram” ycircuit is in one of two states. ytransition on each cycle with each new input, over exactly one arc (edge). yOutput depends on which state the circuit is in.

CS Fall 2007 – Moore and Mealy Machines - 16 Formal Design Process zState Transition Table: zInvent a code to represent states: Let 0 = EVEN state, 1 = ODD state present next state OUT IN state EVEN 0 0 EVEN EVEN 0 1 ODD ODD 1 0 ODD ODD 1 1 EVEN present state (ps) OUT IN next state (ns) Derive logic equations from table (how?): OUT = PS NS = PS xor IN

CS Fall 2007 – Moore and Mealy Machines - 17 Formal Design Process zCircuit Diagram: yXOR gate for ns calculation yDFF to hold present state yno logic needed for output Logic equations from table: OUT = PS NS = PS xor IN ns ps zReview of Design Steps: 1. Circuit functional specification 2. State Transition Diagram 3. Symbolic State Transition Table 4. Encoded State Transition Table 5. Derive Logic Equations 6. Circuit Diagram FFs for state CL for NS and OUT

CS Fall 2007 – Moore and Mealy Machines - 18 Another example zDoor combination lock: ypunch in 3 values in sequence and the door opens; if there is an error the lock must be reset; once the door opens the lock must be reset yinputs: sequence of input values, reset youtputs: door open/close ymemory: must remember combination or always have it available as an input

CS Fall 2007 – Moore and Mealy Machines - 19 closed C1=value & new C2=value & new C3=value & new C1!=value & new C2!=value & new C3!=value & new closed reset not new S1S2S3OPEN ERR open Sequential example: abstract control zFinite-state diagram yStates: 5 states xrepresent point in execution of machine xeach state has outputs yTransitions: 6 from state to state, 5 self transitions, 1 global xchanges of state occur when clock says it’s ok xbased on value of inputs yInputs: reset, new, results of comparisons yOutput: open/closed

CS Fall 2007 – Moore and Mealy Machines - 20 resetnewequalstatestatemuxopen/closed 1–––S1C1closed 00–S1S1C1closed 010S1ERR–closed 011S1S2C2closed 00–S2S2C2closed 010S2ERR–closed 011S2S3C3closed 00–S3S3C3closed 010S3ERR–closed 011S3OPEN–closed 0 – –OPENOPEN– open 0 – –ERRERR– closed next Sequential example (cont’d): finite-state machine zFinite-state machine ygenerate state table (much like a truth-table) closed mux=C1 reset equal & new not equal & new not new S1S2S3OPEN ERR closed mux=C2 equal & new closed mux=C3 equal & new open Symbolic states Encoding?

CS Fall 2007 – Moore and Mealy Machines - 21 Sequential example: encoding zEncode state table ystate can be: S1, S2, S3, OPEN, or ERR xneeds at least 3 bits to encode: 000, 001, 010, 011, 100 xand as many as 5: 00001, 00010, 00100, 01000, xchoose 4 bits: 0001, 0010, 0100, 1000, 0000 zEncode outputs youtput mux can be: C1, C2, or C3 xneeds 2 to 3 bits to encode xchoose 3 bits: 001, 010, 100 youtput open/closed can be: open or closed xneeds 1 or 2 bits to encode xchoose 1 bits: 1, 0 binary One-hot hybrid

CS Fall 2007 – Moore and Mealy Machines - 22 good choice of encoding! mux is identical to last 3 bits of next state open/closed is identical to first bit of state Sequential example (cont’d): encoding zEncode state table ystate can be: S1, S2, S3, OPEN, or ERR xchoose 4 bits: 0001, 0010, 0100, 1000, 0000 youtput mux can be: C1, C2, or C3 xchoose 3 bits: 001, 010, 100 youtput open/closed can be: open or closed xchoose 1 bits: 1, 0 resetnewequalstatestatemuxopen/closed 1––– – – – – – – – 1 0 – – – 1 0 – – – 0 next

CS Fall 2007 – Moore and Mealy Machines - 23 State Minimization zFewer states may mean fewer state variables zHigh-level synthesis may generate many redundant states zTwo state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same zTwo conditions for two states to be equivalent: y1) Output must be the same in both states y2) Must transition to equivalent states for all input combinations

CS Fall 2007 – Moore and Mealy Machines - 24 Sequential Logic Implementation Summary zModels for representing sequential circuits yAbstraction of sequential elements yFinite state machines and their state diagrams yInputs/outputs yMealy, Moore, and synchronous Mealy machines zFinite state machine design procedure yDeriving state diagram yDeriving state transition table yDetermining next state and output functions yImplementing combinational logic